/*
 * Copyright Altera Corporation (C) 2012-2015
 *
 * SPDX-License-Identifier:    BSD-3-Clause
 */

#ifndef _SEQUENCER_DEFINES_H_
#define _SEQUENCER_DEFINES_H_

#define AC_ROM_MR1_MIRR 0000000000100
#define AC_ROM_MR1_OCD_ENABLE
#define AC_ROM_MR2_MIRR 0000000010000
#define AC_ROM_MR3_MIRR 0000000000000
#define AC_ROM_MR0_CALIB
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
#define AC_ROM_MR0_DLL_RESET 0100100110000
#define AC_ROM_MR0_MIRR 0100001001001
#define AC_ROM_MR0 0100000110001
#else
#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
#define AC_ROM_MR0_DLL_RESET 0010100110000
#define AC_ROM_MR0_MIRR 0010001001001
#define AC_ROM_MR0 0010000110001
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AC_ROM_MR1 0000000000100
#define AC_ROM_MR2 0000000001000
#define AC_ROM_MR3 0000000000000
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AFI_CLK_FREQ 534
#else
#define AFI_CLK_FREQ 401
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AFI_RATE_RATIO 1
#define AVL_CLK_FREQ 67
#define BFM_MODE 0
#define BURST2 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define CALIB_LFIFO_OFFSET 8
#define CALIB_VFIFO_OFFSET 6
#else
#define CALIB_LFIFO_OFFSET 7
#define CALIB_VFIFO_OFFSET 5
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define GUARANTEED_READ_BRINGUP_TEST 0
#define HARD_PHY 1
#define HARD_VFIFO 1
#define HPS_HW 1
#define HR_DDIO_OUT_HAS_THREE_REGS 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DELAY_PER_OPA_TAP 234
#else
#define IO_DELAY_PER_OPA_TAP 312
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DM_OUT_RESERVE 0
#define IO_DQDQS_OUT_PHASE_MAX 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DQS_EN_DELAY_MAX 15
#define IO_DQS_EN_DELAY_OFFSET 16
#else
#define IO_DQS_EN_DELAY_MAX 31
#define IO_DQS_EN_DELAY_OFFSET 0
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DQS_EN_PHASE_MAX 7
#define IO_DQS_IN_DELAY_MAX 31
#define IO_DQS_IN_RESERVE 4
#define IO_DQS_OUT_RESERVE 6
#define IO_DQ_OUT_RESERVE 0
#define IO_IO_IN_DELAY_MAX 31
#define IO_IO_OUT1_DELAY_MAX 31
#define IO_IO_OUT2_DELAY_MAX 0
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MARGIN_VARIATION_TEST 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define MEM_ADDR_WIDTH 13
#define READ_VALID_FIFO_SIZE 16
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#else
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_ADDRESS_WIDTH 15
#define RW_MGR_MEM_BANK_WIDTH 3
#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
#define RW_MGR_MEM_CLK_EN_WIDTH 1
#define RW_MGR_MEM_CONTROL_WIDTH 1
#define RW_MGR_MEM_DATA_MASK_WIDTH 5
#define RW_MGR_MEM_DATA_WIDTH 40
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
#define RW_MGR_MEM_ODT_WIDTH 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
#define RW_MGR_MR0_BL 1
#define RW_MGR_MR0_CAS_LATENCY 3
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
#define SKEW_CALIBRATION 0
#define TINIT_CNTR1_VAL 32
#define TINIT_CNTR2_VAL 32
#define TINIT_CNTR0_VAL 132
#define TRESET_CNTR1_VAL 99
#define TRESET_CNTR2_VAL 10
#define TRESET_CNTR0_VAL 132

#endif /* _SEQUENCER_DEFINES_H_ */
