/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/processor.h>

/*#define DEBUG 1*/
/*
 * High Level Configuration Options
 * (easy to change)
 */

/* these hardware addresses are pretty bogus, please change them to
   suit your needs */

/* first ethernet */
#define CONFIG_ETHADDR		00:00:5B:00:6E:8A

#define CONFIG_IPADDR	172.22.2.112
#define CONFIG_SERVERIP 172.22.2.111

#define CONFIG_ENV_OVERWRITE

#if 0

#define CFG_ENV_IS_IN_FLASH	1		/* use Flash for environment vars	*/
#define CFG_ENV_OFFSET		0x70000		/* Last sector of AMD29F040 flash */
#define CFG_ENV_SECT_SIZE	0x10000		/* Total Size of Environment Sector (64kB) */

#else

#define CFG_ENV_IS_IN_NVRAM	1		/* use NVRAM for environment vars	*/
#define CFG_NVRAM_SIZE		(8*1024-16)	/* NVRAM size (8kB), we must protect the clock data (16 bytes) */
#define CFG_ENV_SIZE		0x400		/* Size of Environment vars	(1kB)*/
/*
 * We store the environment in the upper part of the NVRAM. Thus,
 * user applications can use the remaining space for other purposes.
 */
#define CFG_ENV_ADDR		(CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#define CFG_NVRAM_ACCESS_ROUTINE 1		/* This board needs a special routine to access the NVRAM */

#endif

#define CONFIG_75x		1	/* This is a MPC75x		*/
#define CONFIG_BAB750		1	/* ...on an BAB750 board	*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#undef CONFIG_WATCHDOG

/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_ETHER_PORT	0

#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK

#undef	CONFIG_BOOTARGS

#define CONFIG_BOOTCOMMAND						     \
	"bootp 1000000; "						     \
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "  \
	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	"$(netmask):$(hostname):eth0:none; "\
	"bootm"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
				 CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS	 (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE | CFG_CMD_FDC)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

/*
 * choose between COM1 and COM2 as serial console
 */
#define CONFIG_CONS_INDEX	1

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x04000000	/* 0 ... 64 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE    { 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Choose the address mapping scheme for the MPC106 mem controller.
 * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
 */
#define CFG_ADDRESS_MAP_A 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_RAM_ADDR	0x00fd0000     /* above the memtest region */
#define CFG_INIT_RAM_END	0x4000
#define CFG_INIT_DATA_SIZE	64  /* size in bytes reserved for init data */
#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_INIT_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000

/*
 * The mapped position of the flashes is independent from
 * the chosen address map for the MPC106.
 */
#define CFG_FLASH_BASE		0xFFC00000
#define FLASH_BASE0_PRELIM	0xFFC00000
#define FLASH_BASE1_PRELIM	0xFF800000

#define CFG_MONITOR_BASE	TEXT_BASE

#ifdef IN_RAM
  #define CFG_MONITOR_LEN	(4 <<20)	/* if we're running in ram, give us plenty of space for debug info*/
  #undef CFG_MEMTEST
#else
  #define CFG_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor */
  #undef CFG_MEMTEST
#endif

#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */

#define CFG_CPU_CLK		266000000
#define CFG_BUS_CLK		6600000

/*
 * Do NOT change the following table!!! Important mapping information!!
 */
#ifdef CFG_ADDRESS_MAP_A
#define CFG_ISA_MEM		0xC0000000
#define CFG_ISA_IO_BASE_ADDRESS 0x80000000
#define CFG_ISA_IO		CFG_ISA_IO_BASE_ADDRESS
#define CFG_PCI_IO_BASE_ADDRESS 0x81000000
#define CFG_PCI_IO		CFG_PCI_IO_BASE_ADDRESS
#else
#define CFG_ISA_MEM		0xFD000000
#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
#define CFG_ISA_IO		CFG_ISA_IO_BASE_ADDRESS
#define CFG_PCI_IO_BASE_ADDRESS 0xFE800000
#define CFG_PCI_IO		CFG_PCI_IO_BASE_ADDRESS
#endif

/*
 * PCI stuff
 */
#define CONFIG_PCI		/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_AUTO
#define CONFIG_PCI_PNP	/* pci plug-and-play			*/

#define CONFIG_NET_MULTI			/* Multi ethernet cards support */

#define CONFIG_TULIP

/*
 * Do NOT change the following table!!! Important mapping information!!
 */
#ifdef CFG_ADDRESS_MAP_A
#define CFG_PCI_DRAM_OFFSET	0x80000000
#define CFG_60X_PCI_MEM_OFFSET	0xC0000000
#define CFG_60X_PCI_IO_OFFSET	0x80000000
#define CFG_MIN_PCI_MEMADDR1	0x01010000
#define CFG_MIN_PCI_MEMADDR2	0x01010000
#define CFG_PCI_PCI_IOADDR	0x01000000
#else
#define CFG_PCI_DRAM_OFFSET	0x00000000
#define CFG_60X_PCI_MEM_OFFSET	0x00000000
#define CFG_60X_PCI_IO_OFFSET	0xFE000000
#define CFG_MIN_PCI_MEMADDR1	0xF9000000
#define CFG_MIN_PCI_MEMADDR2	0xFA000000
#define CFG_PCI_PCI_IOADDR	0x00800000
#endif

#define CFG_MAX_PCI_DEVICES	32
#define CFG_MAX_PCI_FUNCTIONS	8

/*
 * IDE/ATA stuff
 */
#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_60X_PCI_IO_OFFSET /* base address */
#define CFG_ATA_IDE0_OFFSET	0x1F0	/* default ide0 offset */
#define CFG_ATA_IDE1_OFFSET	0x170	/* default ide1 offset */
#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
#define CFG_ATA_REG_OFFSET	0	/* reg offset */
#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
#undef	CONFIG_IDE_LED	       /* no led for ide supported     */

/*
 * ATAPI support (experimental)
 */
#define CONFIG_ATAPI			/* enable ATAPI Support */


/*
 * SCSI support (experimental) only SYM53C8xx supported
 */
#define CONFIG_SCSI_SYM53C8XX
#define CONFIG_SCSI_DEV_ID	0x000F	/* 53c875 */
#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CFG_SCSI_MAX_SCSI_ID	15	/* maximum SCSI ID (0..6) */
#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#define CFG_SCSI_SPIN_UP_TIME	2
#define CFG_SCSI_SCAN_BUS_REVERSE 0
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION

#define CFG_WINBOND_83C553	1	    /*has a winbond bridge  */
#define CFG_USE_WINBOND_IDE	0	    /*use winbond 83c553 internal ide controller */
#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr */

/*
 * NS87308 Configuration
 */
#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */

#define CFG_NS87308_BADDR_10	1

#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
				  CFG_NS87308_UART2   | \
				  CFG_NS87308_KBC1    | \
				  CFG_NS87308_MOUSE   | \
				  CFG_NS87308_FDC     | \
				  CFG_NS87308_RARP    | \
				  CFG_NS87308_GPIO    | \
				  CFG_NS87308_POWRMAN | \
				  CFG_NS87308_RTC_APC )

#define CFG_NS87308_PS2MOD

#define CFG_NS87308_GPIO_BASE	0x0220
#define CFG_NS87308_PWMAN_BASE	0x0460

/* SuperI/O clock source is 24MHz via X1 */
#define CFG_NS87308_PMC2	0x00

/*
 * set up the NVRAM access registers
 * NVRAM's controlled by the configurable CS line from the 87308
 */
#define CFG_NS87308_CS0_BASE	0x0076
#define CFG_NS87308_CS0_CONF	0x40
#define CFG_NS87308_CS1_BASE	0x0070
#define CFG_NS87308_CS1_CONF	0x1C
#define CFG_NS87308_CS2_BASE	0x0071
#define CFG_NS87308_CS2_CONF	0x1C

/*
 * NS16550 Configuration
 */
#define CFG_NS16550		
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		1843200

#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)

#define CONFIG_RTC_MK48T59

/*
 * Initial BAT mappings
 */

/* do we need the MMU? probably not, but if we do, we must use the BATs */
#undef	CFG_MMU

#ifdef CFG_MMU
/* SDRAM */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT1L
#define CFG_DBAT0U CFG_IBAT1U

/* address range for flashes */
#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U

/* ISA IO space */
#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U

/* ISA memory space */
#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U

#else

#define CFG_IBAT0L 0
#define CFG_IBAT0U 0
#define CFG_DBAT0L CFG_IBAT1L
#define CFG_DBAT0U CFG_IBAT1U

#define CFG_IBAT1L 0
#define CFG_IBAT1U 0
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U

/* ISA IO space */
#define CFG_IBAT2L 0
#define CFG_IBAT2U 0
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U

/* ISA memory space */
#define CFG_IBAT3L 0
#define CFG_IBAT3U 0
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U

#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)  /* Initial Memory map for Linux */

/*
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

/*
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * L2CR setup -- make sure this is right for your board!
 * look in include/mpc74xx.h for the defines used here
 */
/*#define CFG_L2*/
#define L2_INIT	  (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
