/*
 * (C) Copyright 2001
 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
 *
 * Based on code by:
 *
 * Kenneth Johansson ,Ericsson Business Innovation.
 * kenneth.johansson@inn.ericsson.se
 *
 * hacked up by bill hunter. fixed so we could run before
 * serial_init and console_init. previous version avoided this by
 * running out of cache memory during serial/console init, then running
 * this code later.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <asm/processor.h>
#include <i2c.h>
#include <ppc4xx.h>

#ifdef CONFIG_SPD_EEPROM

#define  SDRAM0_CFG_DCE          0x80000000
#define  SDRAM0_CFG_SRE          0x40000000
#define  SDRAM0_CFG_PME          0x20000000
#define  SDRAM0_CFG_MEMCHK       0x10000000
#define  SDRAM0_CFG_REGEN        0x08000000
#define  SDRAM0_CFG_ECCDD        0x00400000
#define  SDRAM0_CFG_EMDULR       0x00200000
#define  SDRAM0_CFG_DRW_SHIFT    (31-6) 
#define  SDRAM0_CFG_BRPF_SHIFT   (31-8) 

#define  SDRAM0_TR_CASL_SHIFT    (31-8)
#define  SDRAM0_TR_PTA_SHIFT     (31-13)
#define  SDRAM0_TR_CTP_SHIFT     (31-15)
#define  SDRAM0_TR_LDF_SHIFT     (31-17)
#define  SDRAM0_TR_RFTA_SHIFT    (31-29)
#define  SDRAM0_TR_RCD_SHIFT     (31-31)

#define  SDRAM0_RTR_SHIFT        (31-15)
#define  SDRAM0_ECCCFG_SHIFT     (31-11)

/* SDRAM0_CFG enable macro  */
#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )   

#define SDRAM0_BXCR_SZ_MASK  0x000e0000
#define SDRAM0_BXCR_AM_MASK  0x0000e000

#define SDRAM0_BXCR_SZ_SHIFT (31-14)
#define SDRAM0_BXCR_AM_SHIFT (31-18)

#define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )   
#define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )   

#ifdef CONFIG_W7O
# define SPD_ERR(x) do { return 0; } while (0)
#else
# define SPD_ERR(x) do { printf(x); hang(); } while (0)
#endif

/*
 * what we really want is 
 * (1/hertz) but we don't want to use floats so multiply with 10E9
 *
 * The error needs to be on the safe side so we want the floor function.
 * This means we get an exact value or we calculate that our bus frequency is
 * a bit faster than it really is and thus we don't progam the sdram controller
 * to run to fast
 */
#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))

/* function prototypes */
int spd_read(uint addr);			/* prototype */


/*
 * This function is reading data from the DIMM module EEPROM over the SPD bus
 * and uses that to program the sdram controller.
 * 
 * This works on boards that has the same schematics that the IBM walnut has.
 *
 * BUG: Don't handle ECC memory
 * BUG: A few values in the TR register is currently hardcoded
 */

long int spd_sdram(void)
{
	int bus_period,tmp,row,col;
	int total_size,bank_size,bank_code;
	int ecc_on;
	int mode = 4;    
	int bank_cnt = 1;
 
	int sdram0_pmit=0x07c00000;
	int sdram0_besr0=-1;
	int sdram0_besr1=-1;
	int sdram0_eccesr=-1;
	int sdram0_ecccfg;

	int sdram0_rtr=0;
	int sdram0_tr=0;

	int sdram0_b0cr;
	int sdram0_b1cr;
	int sdram0_b2cr;
	int sdram0_b3cr;

	int sdram0_cfg=0;
	
	int t_rp;
	int t_rcd;
	int t_rc = 70; /* This value not available in SPD_EEPROM */
	int min_cas = 2;

	/*
	 * Make sure I2C controller is initialized
	 * before continuing.
	 */
	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	/*
	 * Calculate the bus period, we do it this
	 * way to minimize stack utilization.
	 */
    	tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;	/* get FBDV bits */
	tmp = CONFIG_SYS_CLK_FREQ * tmp;	/* get plb freq */
	bus_period = sdram_HZ_to_ns(tmp);	/* get sdram speed */

     	/* Make shure we are using SDRAM */
	if (spd_read(2) != 0x04){
          SPD_ERR("SDRAM - non SDRAM memory module found\n");
     	  }

/*------------------------------------------------------------------
  configure memory timing register

  data from DIMM:
  27	IN Row Precharge Time ( t RP)
  29	MIN RAS to CAS Delay ( t RCD)
  127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
  -------------------------------------------------------------------*/    

     /*
      * first figure out which cas latency mode to use
      * use the min supported mode
      */

	tmp = spd_read(127) & 0x6;
     if(tmp == 0x02){      	   /* only cas = 2 supported */
     	  min_cas = 2;
//     	  t_ck = spd_read(9);
//     	  t_ac = spd_read(10);
	  }
     else if (tmp == 0x04){         /* only cas = 3 supported */
     	  min_cas = 3;
//     	  t_ck = spd_read(9);
//     	  t_ac = spd_read(10);
	  }
     else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
     	  min_cas = 2;
//     	  t_ck = spd_read(23);
//     	  t_ac = spd_read(24);
	  }
     else {
	     SPD_ERR("SDRAM - unsupported CAS latency \n");
	}
     	
     /* get some timing values, t_rp,t_rcd 
     */
     t_rp = spd_read(27);
     t_rcd = spd_read(29);

	
     /* The following timing calcs subtract 1 before deviding.
      * this has effect of using ceiling intead of floor rounding, 
      * and also subtracting 1 to convert number to reg value
      */
     /* set up CASL */
     sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
     /* set up PTA */
     sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
     /* set up CTP */
     tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
     if(tmp<1) SPD_ERR("SDRAM - unsupported prech to act time (Trp)\n");
     sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
     /* set LDF	= 2 cycles, reg value = 1 */
     sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
     /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
	tmp = ((t_rc - 1) / bus_period)-4;
	if(tmp<0)tmp=0;
	if(tmp>6)tmp=6;
	sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
     /* set RCD = t_rcd/bus_period*/
     sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;


/*------------------------------------------------------------------
  configure RTR register
  -------------------------------------------------------------------*/    
     row = spd_read(3);
     col = spd_read(4);
     tmp = spd_read(12) & 0x7f ; /* refresh type less self refresh bit */
     switch(tmp){
	case 0x00:
	  tmp=15625;
	  break;
	case 0x01:
	  tmp=15625/4;
	  break;
	case 0x02:
	  tmp=15625/2;
	  break;
	case 0x03:
	  tmp=15625*2;
	  break;
	case 0x04:
	  tmp=15625*4;
	  break;
	case 0x05:
	  tmp=15625*8;
	  break;
	default:
     	  SPD_ERR("SDRAM - Bad refresh period \n");
	}
	/* convert from nsec to bus cycles */
	tmp = tmp/bus_period;
	sdram0_rtr = (tmp & 0x3ff8)<<  SDRAM0_RTR_SHIFT;

/*------------------------------------------------------------------
  determine the number of banks used
  -------------------------------------------------------------------*/    
	/* byte 7:6 is module data width */
	if(spd_read(7) != 0)
	    SPD_ERR("SDRAM - unsupported module width\n");
	tmp = spd_read(6);
	if (tmp < 32)
	    SPD_ERR("SDRAM - unsupported module width\n");
	else if (tmp < 64)	
	    bank_cnt=1;		/* one bank per sdram side */
	else if (tmp < 73)
	    bank_cnt=2;	/* need two banks per side */
	else if (tmp < 161)
	    bank_cnt=4;	/* need four banks per side */
	else 
	    SPD_ERR("SDRAM - unsupported module width\n");

	/* byte 5 is the module row count (refered to as dimm "sides") */
	tmp = spd_read(5);
	if(tmp==1);
	else if(tmp==2) bank_cnt *=2;
	else if(tmp==4) bank_cnt *=4;
	else bank_cnt = 8; 		/* 8 is an error code */
	
	if(bank_cnt > 4)	/* we only have 4 banks to work with */
	    SPD_ERR("SDRAM - unsupported module rows for this width\n");

	/* now check for ECC ability of module. We only support ECC
	 *   on 32 bit wide devices with 8 bit ECC.
	 */
	if ( (spd_read(11)==2) && ((spd_read(6)==40) || (spd_read(14)==8)) ){ 
	   sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
	   ecc_on = 1;
   	}
	else{
	   sdram0_ecccfg=0;
	   ecc_on = 0;
   	}		
			
/*------------------------------------------------------------------
	calculate total size and do sanity check
  -------------------------------------------------------------------*/    
	/* calculate total size and do sanity check */
	tmp = spd_read(31);
	total_size=1<<22;	/* total_size = 4MB */
	/* now multiply 4M by the smallest device roe density */
	/* note that we don't support asymetric rows */
	while (((tmp & 0x0001) == 0) && (tmp != 0)){
	    total_size= total_size<<1;
	    tmp = tmp>>1;
	    }
	total_size *= spd_read(5);	/* mult by module rows (dimm sides) */
	/* now compute Total size based on address bits */
	tmp = 1 << (row+col);		/* convert rows and cols to size */
	tmp *= spd_read(6)/8;		/* mult by bus width in bytes */
	tmp *= spd_read(17);		/* mult by internal banks */
	/* see if the two methods of calculating size agree */
	if ( tmp != total_size)
	    SPD_ERR("SDRAM - conflicting module memory size\n");
		
/*------------------------------------------------------------------
	map  rows * cols * banks to a mode 
 -------------------------------------------------------------------*/    

	switch( row )
	{
	case 11:
		switch ( col )
		{
		case 8:
			mode=4; /* mode 5 */
			break;
		case 9:
		case 10:
			mode=0; /* mode 1 */
			break;		    
		default:
	     	SPD_ERR("SDRAM - unsupported mode\n");
		}
		break;
	case 12:
		switch ( col )
		{
		case 8:
			mode=3; /* mode 4 */
			break;
		case 9:
		case 10:
			mode=1; /* mode 2 */
			break;
		default:
	     	SPD_ERR("SDRAM - unsupported mode\n");
		}	    
		break;
	case 13:
		switch ( col )
		{
		case 8:
			mode=5; /* mode 6 */
			break;
		case 9:
		case 10:
			if (spd_read(17) ==2 )
				mode=6; /* mode 7 */
			else
				mode=2; /* mode 3 */
			break;
		case 11:
			mode=2; /* mode 3 */
			break;
		default:
	     	SPD_ERR("SDRAM - unsupported mode\n");
		}	    
		break;
	default:
	     SPD_ERR("SDRAM - unsupported mode\n");
	}
     	
/*------------------------------------------------------------------
	using the calculated values, compute the bank 
	config register values. 
 -------------------------------------------------------------------*/    
	sdram0_b1cr = 0;
	sdram0_b2cr = 0;
	sdram0_b3cr = 0;
	
	/* compute the size of each bank */
	bank_size = total_size / bank_cnt;
	/* convert bank size to bank size code for ppc4xx 
		by takeing log2(bank_size) - 22 */
	tmp=bank_size; 		/* start with tmp = bank_size */
	bank_code=0;			/* and bank_code = 0 */
	while (tmp>1){ 		/* this takes log2 of tmp */
		bank_code++;		/* and stores result in bank_code */
		tmp=tmp>>1;
		}				/* bank_code is now log2(bank_size) */
	bank_code-=22;				/* subtract 22 to get the code */

	tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
    	sdram0_b0cr = (bank_size) * 0 | tmp;
    	if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
    	if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
    	if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;

    
	/* 
	 *   enable sdram controller DCE=1
	 *  enable burst read prefetch to 32 bytes BRPF=2
	 *  leave other functions off
	 */

/*------------------------------------------------------------------
	now that we've done our calculations, we are ready to 
	program all the registers. 
 -------------------------------------------------------------------*/    


#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
	/* disable memcontroller so updates work */
	sdram0_cfg = 0;       	   
	mtsdram0( mem_mcopt1, sdram0_cfg );

	mtsdram0( mem_besra , sdram0_besr0 );
	mtsdram0( mem_besrb , sdram0_besr1 );
	mtsdram0( mem_rtr   , sdram0_rtr );
	mtsdram0( mem_pmit  , sdram0_pmit );
	mtsdram0( mem_mb0cf , sdram0_b0cr );
	mtsdram0( mem_mb1cf , sdram0_b1cr );
	mtsdram0( mem_mb2cf , sdram0_b2cr );
	mtsdram0( mem_mb3cf , sdram0_b3cr );
	mtsdram0( mem_sdtr1 , sdram0_tr );
	mtsdram0( mem_ecccf , sdram0_ecccfg );
	mtsdram0( mem_eccerr, sdram0_eccesr );

	/* SDRAM have a power on delay,  500 micro should do */
	udelay(500);
	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
	if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
	mtsdram0( mem_mcopt1, sdram0_cfg );


	/* kernel 2.4.2 from mvista has a bug with memory over 128MB */
#ifdef MVISTA_MEM_BUG
	if (total_size > 128*1024*1024 )
		total_size=128*1024*1024;
#endif	
	return (total_size);
}

int spd_read(uint addr)
{
	char data[2];

	if (i2c_read(0x50, addr, 1, data, 1) == 0)
		return (int)data[0];
	else
		return 0;
}

#endif /* CONFIG_DIMM_EEPROM */
