/*
 * (C) Copyright 2000
 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH:
 *		Added initialisation of additional logical devices on the chip.
 */
 
#include <config.h>

#include "ns87308.h"
#include "ns16550.h"			/* to configure the 87308's internal 16550's */
#include <asm/mc146818rtc.h>	/* to configure 87308's RTC */

void initialise_ns87308 (void)
{
	unsigned char data;

	/*
	 * Switch floppy drive to PS/2 mode.
	 */
	read_pnp_config(SUPOERIO_CONF1, &data);
	data &= 0xFB;
	write_pnp_config(SUPOERIO_CONF1, data);
	
	PNP_SET_DEVICE_BASE(LDEV_UART1, COM1);
	PNP_SET_DEVICE_BASE(LDEV_UART2, COM2);

	PNP_SET_DEVICE_BASE(LDEV_KBC1, KBC1_BASE);
	write_pnp_config(LUN_CONFIG_REG, 0);
	write_pnp_config(CBASE_HIGH, 0x00);
	write_pnp_config(CBASE_LOW, 0x64);
	
	PNP_ACTIVATE_DEVICE(LDEV_MOUSE);
    
	PNP_SET_DEVICE_BASE(LDEV_FDC, FDC_BASE);
	write_pnp_config(LUN_CONFIG_REG, 0x40);

	PNP_SET_DEVICE_BASE(LDEV_PARP, LPT_BASE);
	PNP_SET_DEVICE_BASE(LDEV_GPIO, GPIO_BASE);

	PNP_SET_DEVICE_BASE(LDEV_RTC_APC, RTC_PORT(0));
	PNP_SET_DEVICE_BASE(LDEV_POWRMAN, PWMAN_BASE);
    
	/* Enable all units */
	pci_writeb(0x00, CFG_ISA_IO + PWMAN_BASE);
	eieio();
	pci_writeb(0x7d, CFG_ISA_IO + PWMAN_BASE + 1);

	pci_writeb(0x01, CFG_ISA_IO + PWMAN_BASE);
	eieio();
	pci_writeb(0x87, CFG_ISA_IO + PWMAN_BASE + 1);
    
	/* SuperI/O clock source is 24MHz via X1 */
	pci_writeb(0x03, CFG_ISA_IO + PWMAN_BASE);
	eieio();
	pci_writeb(0x00, CFG_ISA_IO + PWMAN_BASE + 1);
	
	/*
	 * set up the NVRAM access registers
	 * NVRAM's controlled by the configurable CS line from the 87308
	 */
	PNP_PGCS_CSLINE_BASE(0, 0x76);
	PNP_PGCS_CSLINE_CONF(0, 0x40);
	PNP_PGCS_CSLINE_BASE(1, 0x70);
	PNP_PGCS_CSLINE_CONF(1, 0x1C);
	PNP_PGCS_CSLINE_BASE(2, 0x71);
	PNP_PGCS_CSLINE_CONF(2, 0x1C);
}
