/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _MPC106_PCI_H
#define _MPC106_PCI_H

#ifndef DEFS_ONLY
typedef struct pciHeaderDevice {
    short	vendorId;	/* vendor ID */
    short	deviceId;	/* device ID */
    short	command;	/* command register */
    short	status;		/* status register */
    char	revisionId;	/* revision ID */
    char	classCode;	/* class code */
    char	subClass;	/* sub class code */
    char	progIf;		/* programming interface */
    char	cacheLine;	/* cache line */
    char	latency;	/* latency time */
    char	headerType;	/* header type */
    char	bist;		/* BIST */
    int		base0;		/* base address 0 */
    int		base1;		/* base address 1 */
    int		base2;		/* base address 2 */
    int		base3;		/* base address 3 */
    int		base4;		/* base address 4 */
    int		base5;		/* base address 5 */
    int		cis;		/* cardBus CIS pointer */
    short	subVendorId;	/* sub system vendor ID */
    short	subSystemId;	/* sub system ID */
    int		romBase;	/* expansion ROM base address */
    int		reserved0;	/* reserved */
    int		reserved1;	/* reserved */
    char	intLine;	/* interrupt line */
    char	intPin;		/* interrupt pin */
    char	minGrant;	/* min Grant */
    char	maxLatency;	/* max Latency */
} PCI_HEADER_DEVICE;

typedef struct pciHeaderBridge {
    short	vendorId;	/* vendor ID */
    short	deviceId;	/* device ID */
    short	command;	/* command register */
    short	status;		/* status register */
    char	revisionId;	/* revision ID */
    char	classCode;	/* class code */
    char	subClass;	/* sub class code */
    char	progIf;		/* programming interface */
    char	cacheLine;	/* cache line */
    char	latency;	/* latency time */
    char	headerType;	/* header type */
    char	bist;		/* BIST */
    int		base0;		/* base address 0 */
    int		base1;		/* base address 1 */
    char	priBus;		/* primary bus number */
    char	secBus;		/* secondary bus number */
    char	subBus;		/* subordinate bus number */
    char	secLatency;	/* secondary latency timer */
    char	ioBase;		/* IO base */
    char	ioLimit;	/* IO limit */
    short	secStatus;	/* secondary status */
    short	memBase;	/* memory base */
    short	memLimit;	/* memory limit */
    short	preBase;	/* prefetchable memory base */
    short	preLimit;	/* prefetchable memory limit */
    int		preBaseUpper;	/* prefetchable memory base upper 32 bits */
    int		preLimitUpper;	/* prefetchable memory base upper 32 bits */
    short	ioBaseUpper;	/* IO base upper 16 bits */
    short	ioLimitUpper;	/* IO limit upper 16 bits */
    int		reserved;	/* reserved */
    int		romBase;	/* expansion ROM base address */
    char	intLine;	/* interrupt line */
    char	intPin;		/* interrupt pin */
    short	control;	/* bridge control */
} PCI_HEADER_BRIDGE;

#endif	/*  DEFS_ONLY */


/*
 * Defines for the MPC106 PCI Config address and data registers followed by
 * defines for the standard PCI device configuration header.
 */
 
#define PCIDEVID_MPC106 	0x0

/*
 * MPC106 Registers
 */
#define	MPC106_REG			0x80000000

#ifdef CFG_ADDRESS_MAP_A
#define MPC106_REG_ADDR 	0x80000cf8
#define	MPC106_REG_DATA		0x80000cfc
#else
#define MPC106_REG_ADDR 	0xfec00cf8
#define	MPC106_REG_DATA		0xfee00cfc
#endif

#define CMD_SERR		0x0100
#define PCI_CMD_MASTER	0x0004
#define PCI_CMD_MEMEN	0x0002
#define PCI_CMD_IOEN	0x0001

#define PCI_STAT_NO_RSV_BITS	0xffff

#define PCI_BUSNUM       0x40
#define PCI_SUBBUSNUM    0x41
#define PCI_DISCOUNT     0x42

#define PCI_PICR1			0xA8
#define PICR1_CF_CBA(value)		 ((value & 0xff) << 24)
#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
#define PICR1_PROC_TYPE_603	0x40000
#define PICR1_PROC_TYPE_604	0x60000
#define PICR1_MCP_EN		0x800
#define PICR1_CF_DPARK		0x200
#define PICR1_CF_LOOP_SNOOP	0x10
#define PICR1_CF_APARK		0x8
#define PICR1_ADDRESS_MAP	0x10000
#define PICR1_XIO_MODE		0x80000

#define PCI_PICR2			0xAC
#define PICR2_CF_SNOOP_WS(value)	 ((value & 0x3) << 18)
#define PICR2_CF_FLUSH_L2	0x10000000
#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
#define PICR2_CF_APHASE_WS(value)	 ((value & 0x3) << 2)
#define PICR2_L2_EN			0x40000000
#define PICR2_L2_UPDATE_EN	0x80000000

/*
 * PCI-PCI bridge header
 */
#define PCIPCI_PRIMARYBUS       0x18
#define PCIPCI_SECONDARYBUS     0x19
#define PCIPCI_SUBORDINATEBUS   0x1A
#define PCIPCI_SECONDARYLATENCY 0x1B
#define PCIPCI_IOBASE           0x1C
#define PCIPCI_IOLIMIT          0x1D
#define PCIPCI_SECONDARYSTATUS  0x1E
#define PCIPCI_MEMBASE          0x20
#define PCIPCI_MEMLIMIT         0x22
#define PCIPCI_PREFETCHMEMBASE  0x24
#define PCIPCI_PREFETCHMEMLIMIT 0x26
#define PCIPCI_IOBASEUPPER16    0x30
#define PCIPCI_IOLIMITUPPER16   0x32

/*
 * Standard device configuration register offsets
 * Note that only modulo-4 addresses are written to the address register
 */
#define	PCI_CFG_VENDOR_ID	0x00
#define	PCI_CFG_DEVICE_ID	0x02
#define	PCI_CFG_COMMAND		0x04
#define	PCI_CFG_STATUS		0x06
#define	PCI_CFG_REVISION	0x08
#define	PCI_CFG_PROGRAMMING_IF	0x09
#define	PCI_CFG_SUBCLASS	0x0a
#define	PCI_CFG_CLASS		0x0b
#define	PCI_CFG_CACHE_LINE_SIZE	0x0c
#define	PCI_CFG_LATENCY_TIMER	0x0d
#define	PCI_CFG_HEADER_TYPE	0x0e
#define	PCI_CFG_BIST		0x0f
#define	PCI_CFG_BASE_ADDRESS_0	0x10
#define	PCI_CFG_BASE_ADDRESS_1	0x14
#define	PCI_CFG_BASE_ADDRESS_2	0x18
#define	PCI_CFG_BASE_ADDRESS_3	0x1c
#define	PCI_CFG_BASE_ADDRESS_4	0x20
#define	PCI_CFG_BASE_ADDRESS_5	0x24
#define	PCI_CFG_CIS		0x28
#define	PCI_CFG_SUB_VENDER_ID	0x2c
#define	PCI_CFG_SUB_SYSTEM_ID	0x2e
#define	PCI_CFG_EXPANSION_ROM	0x30
#define	PCI_CFG_RESERVED_0	0x34
#define	PCI_CFG_RESERVED_1	0x38
#define	PCI_CFG_DEV_INT_LINE	0x3c
#define	PCI_CFG_DEV_INT_PIN	0x3d
#define	PCI_CFG_MIN_GRANT	0x3e
#define	PCI_CFG_MAX_LATENCY	0x3f
#define PCI_CFG_SPECIAL_USE     0x41
#define PCI_CFG_MODE            0x43


/*
 * PCI-to-PCI bridge configuration register offsets
 * Note that only modulo-4 addresses are written to the address register
 */
#define	PCI_CFG_PRIMARY_BUS	0x18
#define	PCI_CFG_SECONDARY_BUS	0x19
#define	PCI_CFG_SUBORDINATE_BUS	0x1a
#define	PCI_CFG_SEC_LATENCY	0x1b
#define	PCI_CFG_IO_BASE		0x1c
#define	PCI_CFG_IO_LIMIT	0x1d
#define	PCI_CFG_SEC_STATUS	0x1e
#define	PCI_CFG_MEM_BASE	0x20
#define	PCI_CFG_MEM_LIMIT	0x22
#define	PCI_CFG_PRE_MEM_BASE	0x24
#define	PCI_CFG_PRE_MEM_LIMIT	0x26
#define	PCI_CFG_PRE_MEM_BASE_U	0x28
#define	PCI_CFG_PRE_MEM_LIMIT_U	0x2c
#define	PCI_CFG_IO_BASE_U	0x30
#define	PCI_CFG_IO_LIMIT_U	0x32
#define	PCI_CFG_ROM_BASE	0x38
#define	PCI_CFG_BRG_INT_LINE	0x3c
#define	PCI_CFG_BRG_INT_PIN	0x3d
#define	PCI_CFG_BRIDGE_CONTROL	0x3e


/*
 * Memory controller
 */
#define MPC106_MCCR1		0xF0
#define MCCR1_TYPE_EDO		0x00020000
#define MCCR1_BK0_9BITS		0x0
#define MCCR1_BK0_10BITS	0x1
#define MCCR1_BK0_11BITS	0x2
#define MCCR1_BK0_12BITS	0x3
#define MCCR1_BK1_9BITS		0x0
#define MCCR1_BK1_10BITS	0x4
#define MCCR1_BK1_11BITS	0x8
#define MCCR1_BK1_12BITS	0xC
#define MCCR1_BK2_9BITS		0x00
#define MCCR1_BK2_10BITS	0x10
#define MCCR1_BK2_11BITS	0x20
#define MCCR1_BK2_12BITS	0x30
#define MCCR1_BK3_9BITS		0x00
#define MCCR1_BK3_10BITS	0x40
#define MCCR1_BK3_11BITS	0x80
#define MCCR1_BK3_12BITS	0xC0
#define MCCR1_MEMGO			0x00080000

#define MPC106_MCCR2		0xF4
#define MPC106_MCCR3		0xF8
#define MPC106_MCCR4		0xFC

#define MPC106_MSAR1		0x80
#define MPC106_EMSAR1		0x88
#define MPC106_EMSAR2		0x8C
#define MPC106_MEAR1		0x90
#define MPC106_EMEAR1		0x98
#define MPC106_EMEAR2		0x9C

#define MPC106_MBER			0xA0
#define MBER_BANK0			0x1
#define MBER_BANK1			0x2
#define MBER_BANK2			0x4
#define MBER_BANK3			0x8


#ifndef DEFS_ONLY

unsigned int    PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width);
int				PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width);
int             PCI_Scan(int BusNum);
void            PCI_Config_Device(int BusDevFunc, int NumBaseAddr);
void            PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr);
void            PCI_Config_Bridge(int BusDevFunc);
int             PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID);
void            PCI_Header_Show(int BusDevFunc);
void            PCI_Dheader_Print(PCI_HEADER_DEVICE * pD);
void            PCI_Bheader_Print(PCI_HEADER_BRIDGE * pB);

/*
 * memory mapping functions
 */
unsigned long	phys_to_bus(void*);
void *bus_to_phys(unsigned long);

#endif	/*  DEFS_ONLY */


#endif

