/*
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
 *  Copyright (C) 2001	Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 *			Andreas Heppel <aheppel@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*  ppcboot - Startup Code for PowerPC based Embedded Boards
 *
 *
 *  The processor starts at 0xfff00100 and the code is executed
 *  from flash. The code is organized to be at an other address
 *  in memory, but as long we don't jump around before relocating.
 *  board_init lies at a quite high address and when the cpu has
 *  jumped there, everything is ok.
 */
 
/* Although this file was originally dvelopped for the MPC750 CPU,
 * it should be possible to use it for MPC740/MPC7400 CPUs as well
 * since there are anly small differences in the basic operation.
 * However, the code has been tested with an MPC750 CPU only.
 */

#include <config.h>
#include <mpc75x.h>
#include "version.h"

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't want the  MMU yet.
*/
#undef	MSR_KERNEL
/* Machine Check and Recoverable Interr. */
#define MSR_KERNEL ( MSR_ME | MSR_RI )

	
/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(MessageBlock)
/*	GOT_ENTRY(spdRead)*/
	GOT_ENTRY(_end)
	GOT_ENTRY(.bss)
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956		/* PPCBOOT Magic Number		*/

	.globl	version_string
version_string:
	.ascii PPCBOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH */
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x10

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
	b	boot_warm

	/* the boot code is located below the exception table */
	
	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

	/* No FPU on MPC8xx.  This exception is not supposed to happen.
	*/
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)

	. = 0xc00
/*
 * r0 - SYSCALL number
 * r3-... arguments
 */
SystemCall:
	addis	r11,r0,0		/* get functions table addr */
	ori	r11,r11,0		/* Note: this code is patched in trap_init */
	addis	r12,r0,0		/* get number of functions */
	ori	r12,r12,0

	cmplw	0, r0, r12
	bge	1f
	
	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
	add	r11,r11,r0
	lwz	r11,0(r11)

	li	r12,0xd00-4*3		/* save LR & SRRx */
	mflr	r0
	stw	r0,0(r12)
	mfspr	r0,SRR0
	stw	r0,4(r12)
	mfspr	r0,SRR1
	stw	r0,8(r12)

	li	r12,0xc00+_back-SystemCall
	mtlr	r12
	mtspr	SRR0,r11

1:	SYNC
	rfi

_back:

	mfmsr	r11			/* Disable interrupts */
	li	r12,0
	ori	r12,r12,MSR_EE
	andc	r11,r11,r12
	SYNC				/* Some chip revs need this... */
	mtmsr	r11
	SYNC

	li	r12,0xd00-4*3		/* restore regs */
	lwz	r11,0(r12)
	mtlr	r11
	lwz	r11,4(r12)
	mtspr	SRR0,r11
	lwz	r11,8(r12)
	mtspr	SRR1,r11

	SYNC
	rfi

	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
	 * for all unimplemented and illegal instructions.
	 */
	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)

	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)

	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)

	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)

	/* PPC documentation says that the vector table ends at 0x3000 */
	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000

boot_cold:
boot_warm:
	/* disable everything */
	li	r0, 0
	
	/* hardware imlementation register */
	mtspr	HID0, r0
	sync
	mtmsr	0

	/* invalidate BATs */
	mtspr	IBAT0U, r0
	mtspr	IBAT1U, r0
	mtspr	IBAT2U, r0
	mtspr	IBAT3U, r0
	isync
	mtspr	DBAT0U, r0
	mtspr	DBAT1U, r0
	mtspr	DBAT2U, r0
	mtspr	DBAT3U, r0
	isync

	/* Turn off data and instruction cache control bits */
	mfspr   r3, HID0
	isync
	rlwinm	r4, r3, 0, 18, 15
	sync
	isync
	mtspr	HID0, r4
	isync

	/* invalidate the MPU's data/instruction caches */
	ori	r3, r3, 0xCC00
	or	r4, r4, r3
	isync
	mtspr   HID0, r4
	andc	r4, r4, r3
	isync
	mtspr	HID0, r4
	isync
	
	ori	r4, r4, 0x8800

    /*
     * The setting of the instruction cache enable (ICE) bit must be
     * preceded by an isync instruction to prevent the cache from being
     * enabled or disabled while an instruction access is in progress.
     */
	isync

    mtspr   HID0, r4
	isync

#if defined(CFG_L2) && (defined(CONFIG_75x) || defined(CONFIG_74xx))
	/* init the L2 cache */
	addis	r3, r0, L2_INIT@h
	ori	r3, r3, L2_INIT@l
	mtspr	l2cr, r3

	/* invalidate the L2 cache */
	sync
	oris	r3, r3, L2CR_L2I@h
	mtspr	l2cr, r3
	sync

invl2:
	mfspr	r3, l2cr
	andi.	r3, r3, L2CR_L2IP
	bne	invl2

	/* turn off the global invalidate bit */
	mfspr	r3, l2cr
	rlwinm	r3, r3, 0, 11, 9
	mtspr	l2cr, r3
#endif

	/* setup the bats */
	bl	setup_bats
	sync

#if CFG_MMU
	/*enable address translation */
	bl	enable_addr_trans
	sync
#endif

	/*
	 * Calculate absolute address in FLASH and jump there
	 *------------------------------------------------------*/
	lis	r3, CFG_MONITOR_BASE@h
	ori	r3, r3, CFG_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:
	/* let the C-code set up the rest			*/
	/*							*/
	/* Be careful to keep code relocatable !		*/
	/*------------------------------------------------------*/

	GET_GOT			/* initialize GOT access	*/

	/*
	 * Change the address map if this is configured
	 */
	bl set_address_map

	/*
	 * Since the 7xx/7xxx CPUs do not have any RAM on chip
	 * we cannot wait to initialise the RAM during board_init_f.
	 * We need some RAM before we can run C code.
	 */
	bl ram_init
	
	/* set up r1 (SP) */
	lis		r1,CFG_INIT_RAM_ADDR@h
   	ori		r1,r1,CFG_INIT_SP_OFFSET	/* set up the stack in SDRAM */
	stwu    r1, -8(r1)					/* make room for stack frame header */

	/* run low-level CPU init code     (from Flash)	*/
	bl	cpu_init_f

	/* r3: BOOTFLAG */
	mr	r3, r21
	/* run 1st part of board init code (from Flash)   */
	bl	board_init_f

	/* NOTREACHED */
	
	/* setup_bats - set them up to some initial state */
	.globl	setup_bats
setup_bats:

	/*
	 * We need the bats only, if we use the MMU, otherwise they may remain
	 * invalidated
	 */
#ifdef CFG_MMU
	addis	r0, r0, 0x0000

	/* IBAT 0 */
	addis	r4, r0, CFG_IBAT0L@h
	ori	r4, r4, CFG_IBAT0L@l
	addis	r3, r0, CFG_IBAT0U@h
	ori	r3, r3, CFG_IBAT0U@l
	mtspr	IBAT0L, r4
	mtspr	IBAT0U, r3
	isync

	/* DBAT 0 */
	addis	r4, r0, CFG_DBAT0L@h
	ori	r4, r4, CFG_DBAT0L@l
	addis	r3, r0, CFG_DBAT0U@h
	ori	r3, r3, CFG_DBAT0U@l
	mtspr	DBAT0L, r4
	mtspr	DBAT0U, r3
	isync

	/* IBAT 1 */
	addis	r4, r0, CFG_IBAT1L@h
	ori	r4, r4, CFG_IBAT1L@l
	addis	r3, r0, CFG_IBAT1U@h
	ori	r3, r3, CFG_IBAT1U@l
	mtspr	IBAT1L, r4
	mtspr	IBAT1U, r3
	isync

	/* DBAT 1 */
	addis	r4, r0, CFG_DBAT1L@h
	ori	r4, r4, CFG_DBAT1L@l
	addis	r3, r0, CFG_DBAT1U@h
	ori	r3, r3, CFG_DBAT1U@l
	mtspr	DBAT1L, r4
	mtspr	DBAT1U, r3
	isync

	/* IBAT 2 */
	addis	r4, r0, CFG_IBAT2L@h
	ori	r4, r4, CFG_IBAT2L@l
	addis	r3, r0, CFG_IBAT2U@h
	ori	r3, r3, CFG_IBAT2U@l
	mtspr	IBAT2L, r4
	mtspr	IBAT2U, r3
	isync

	/* DBAT 2 */
	addis	r4, r0, CFG_DBAT2L@h
	ori	r4, r4, CFG_DBAT2L@l
	addis	r3, r0, CFG_DBAT2U@h
	ori	r3, r3, CFG_DBAT2U@l
	mtspr	DBAT2L, r4
	mtspr	DBAT2U, r3
	isync

	/* IBAT 3 */
	addis	r4, r0, CFG_IBAT3L@h
	ori	r4, r4, CFG_IBAT3L@l
	addis	r3, r0, CFG_IBAT3U@h
	ori	r3, r3, CFG_IBAT3U@l
	mtspr	IBAT3L, r4
	mtspr	IBAT3U, r3
	isync

	/* DBAT 3 */
	addis	r4, r0, CFG_DBAT3L@h
	ori	r4, r4, CFG_DBAT3L@l
	addis	r3, r0, CFG_DBAT3U@h
	ori	r3, r3, CFG_DBAT3U@l
	mtspr	DBAT3L, r4
	mtspr	DBAT3U, r3
	isync
#endif

	/* now invalidate the TLBs */
	addis	r3, 0, 0x0000
#ifdef CONFIG_74x
	addis	r5, 0, 0x2    /* upper bound of 0x00020000 for 740 (603e) */
#endif
#if defined(CONFIG_75x) || defined(CONFIG_74xx)
	addis	r5, 0, 0x4    /* upper bound of 0x00040000 for 750/7400 */
#endif
	isync

tlblp:
	tlbie	r3
	sync
	addi	r3, r3, 0x1000
	cmp	0, 0, r3, r5
	blt tlblp

	blr

	.globl enable_addr_trans
enable_addr_trans:
	/* enable address translation */
	mfmsr	r5
	ori	r5, r5, (MSR_IR | MSR_DR)
	mtmsr	r5
	isync
	blr

	.globl disable_addr_trans
disable_addr_trans:
	/* disable address translation */
	mfmsr	r5
	andi.	r5, r5, (~(MSR_IR | MSR_DR) & 0xFFFF)
	mtmsr	r5
	isync
	blr
	

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r29		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r29,r29,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r29
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/* Cache functions.  XXX fix these, I think they're broken [josh].
*/
	.globl	icache_enable
icache_enable:
	mfspr	r3, HID0
	ori	r3, r3, (HID0_ICE | HID0_ICFI)
	isync
	mtspr	HID0, r3
	blr

	.globl	icache_disable
icache_disable:
	mfspr	r3, HID0
	li	r4, 0
	ori	r4, r4, HID0_ICE
	andc	r3, r3, r4
	isync
	mtspr	HID0, r3
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, HID0
	andi.	r3, r3, HID0_ICE
	blr

	.globl	dcache_enable
dcache_enable:
	mfspr	r3, HID0
	ori	r3, r3, (HID0_DCI | HID0_DCE)
	sync
	mtspr	HID0, r3
	blr

	.globl	dcache_disable
dcache_disable:
	mfspr	r3, HID0
	li	r4, HID0_DCE
	andc	r3, r3, r4
	sync
	mtspr	HID0, r3
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, HID0
	andi.	r3, r3, HID0_DCE
	blr

	.globl	l2_enable
l2_enable:
	addis	r3, r0, L2_ENABLE@h
	ori	r3, r3, L2_ENABLE@l
	mtspr	l2cr, r3
	blr	
	
	.globl	dc_read
dc_read:
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr

/*-----------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, bd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer		*/
	mr	r9,  r4		/* Save copy of Board Info pointer	*/
	mr	r10, r5		/* Save copy of Destination Address	*/

	mr	r3,  r5				/* Destination Address	*/
	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CFG_MONITOR_BASE@l
	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
	ori	r5, r5, CFG_MONITOR_LEN@l
	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4	/* dest addr - moni base */

	/* First our own GOT */
	add	r14, r14, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */
	
	cmplw	cr1,r3,r4	/* cmp dest addr /w src addr */
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	7f		/* Protect against 0 count		*/
	mtctr	r0		/* ctr contains now moni len in DWORDS	*/
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:
	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	cmplw	r4,r5
	dcbst	0,r4
	add	r4,r4,r6
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	cmplw	r4,r5
	icbi	0,r4
	add	r4,r4,r6
	blt	6b

7:
	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:
	/*
	 * Relocation Function, r14 point to got2+0x8000
	 *
         * Adjust got2 pointers, no need to check for 0, this code
         * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	add	r0,r0,r11
	stw	r0,0(r3)
	bdnz	1b
	
	/*
     * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */	
2:	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(.bss)
	lwz	r4,GOT(_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:
	mr	r3, r9		/* Board Info pointer		*/
	mr	r4, r10		/* Destination Address		*/

	bl	board_init_r

	/* Problems accessing "end" in C, so do it here */
	.globl	get_endaddr
get_endaddr:
	lwz	r3,GOT(_end)
	blr

	.globl	get_startaddr
get_startaddr:
	lwz	r3,GOT(_start)
	blr

	.globl	get_msgblk
get_msgblk:
	lwz	r3,GOT(MessageBlock)
	blr

/*	.globl	get_spdread
get_spdread:
	lwz	r3,GOT(spdRead)
	blr

*/
	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */

	mflr	r4			/* save link register		*/
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b
	
	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr

	/*
	 * Function: relocate entries for one exception vector
	 */
trap_reloc:
	lwz	r0, 0(r7)		/* hdlr ...			*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 0(r7)

	lwz	r0, 4(r7)		/* int_return ...		*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 4(r7)

	sync
	isync

	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     in8 */
/*  Description:  Input 8 bits */
/* ------------------------------------------------------------------------------- */
	.globl  in8
in8:
	lbz     r3,0(r3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     in16 */
/*  Description:  Input 16 bits */
/* ------------------------------------------------------------------------------- */
	.globl  in16
in16:
	lhz     r3,0(r3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     in16r */
/*  Description:  Input 16 bits and byte reverse */
/* ------------------------------------------------------------------------------- */
	.globl  in16r
in16r:
	lhbrx   r3,0,r3
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     in32 */
/*  Description:  Input 32 bits */
/* ------------------------------------------------------------------------------- */
	.globl  in32
in32:
	lwz     3,0(3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     in32r */
/*  Description:  Input 32 bits and byte reverse */
/* ------------------------------------------------------------------------------- */
    .globl  in32r
in32r:
	lwbrx   r3,0,r3
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     out8 */
/*  Description:  Output 8 bits */
/* ------------------------------------------------------------------------------- */
	.globl  out8
out8:
	stb     r4,0(r3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     out16 */
/*  Description:  Output 16 bits */
/* ------------------------------------------------------------------------------- */
	.globl  out16
out16:
	sth     r4,0(r3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     out16r */
/*  Description:  Byte reverse and output 16 bits */
/* ------------------------------------------------------------------------------- */
	.globl  out16r
out16r:
	sthbrx  r4,0,r3
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     out32 */
/*  Description:  Output 32 bits */
/* ------------------------------------------------------------------------------- */
	.globl  out32
out32:
	stw     r4,0(r3)
	sync
	blr

/* ------------------------------------------------------------------------------- */
/*  Function:     out32r */
/*  Description:  Byte reverse and output 32 bits */
/* ------------------------------------------------------------------------------- */
	.globl  out32r
out32r:
	stwbrx  r4,0,r3
	sync
	blr

