/*
 * (C) Copyright 2001
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <asm/processor.h>
#include <command.h>

/* ------------------------------------------------------------------------- */

#define MAX_ONES               226
#define FPGA_PRG_SLEEP         32        /* fpga program sleep-time */

#define IBM405GP_GPIO0_OR      0xef600700  /* GPIO Output */
#define IBM405GP_GPIO0_TCR     0xef600704  /* GPIO Three-State Control */
#define IBM405GP_GPIO0_ODR     0xef600718  /* GPIO Open Drain */
#define IBM405GP_GPIO0_IR      0xef60071c  /* GPIO Input */

#define FPGA_PRG               0x04000000  /* FPGA program pin (ppc output) */
#define FPGA_CLK               0x02000000  /* FPGA clk pin (ppc output)     */
#define FPGA_DATA              0x01000000  /* FPGA data pin (ppc output)    */
#define FPGA_DONE              0x00800000  /* FPGA done pin (ppc input)     */
#define FPGA_INIT              0x00400000  /* FPGA init pin (pcc input)     */

#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */

#define SET_FPGA(data)         out32(IBM405GP_GPIO0_OR, data)

#define FPGA_WRITE_1 {                                                    \
        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

#define FPGA_WRITE_0 {                                                    \
        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
        SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
        SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */


static int fpga_boot_compressed(void)
{
  int i,index,len;
  unsigned char b;
  int size = sizeof(fpgadata);
  int bit;
  int start;

  /* display infos on fpgaimage */
  index = 15;
  for (i=0; i<4; i++)
    {
      len = fpgadata[index];
#ifdef FPGA_DEBUG
      printf("FPGA: %s\n", &(fpgadata[index+1]));
#endif
      index += len+3;
    }

  /* search for preamble 0xFF2X */
  for (index = 0; index < size-1 ; index++)
    {
      if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
	break;
    }
  index += 2;

#ifdef FPGA_DEBUG
  printf("FPGA: COMPRESSED configdata starts at position 0x%x\n",index);
  printf("FPGA: length of fpga-data %d\n", size-index);
#endif

  /*
   * Setup port pins for fpga programming
   */
  out32(IBM405GP_GPIO0_ODR, 0x00000000);                       /* no open drain pins      */
  out32(IBM405GP_GPIO0_TCR, FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* setup for output        */
  out32(IBM405GP_GPIO0_OR,  FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set output pins to high */

#ifdef FPGA_DEBUG
  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
#endif

  /*
   * Init fpga by asserting and deasserting PROGRAM*
   */
  SET_FPGA(FPGA_CLK | FPGA_DATA);

  /* Setup timeout timer */
  start = get_timer(0);

  /* Wait for FPGA init line low */
  while (in32(IBM405GP_GPIO0_IR) & FPGA_INIT)
    {
      /* Check for timeout - 100us max, so use 3ms */
      if (get_timer(start) > 3)
        {
#ifdef FPGA_DEBUG
          printf("FPGA: Booting failed!\n");
#endif
          return ERROR_FPGA_PRG_INIT_LOW;
        }
    }

#ifdef FPGA_DEBUG
  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
#endif

  /* deassert PROGRAM* */
  SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);

  /* Wait for FPGA end of init period .  */
  while (!(in32(IBM405GP_GPIO0_IR) & FPGA_INIT))
    {
      /* Check for timeout */
      if (get_timer(start) > 3)
        {
#ifdef FPGA_DEBUG
          printf("FPGA: Booting failed!\n");
#endif
          return ERROR_FPGA_PRG_INIT_HIGH;
        }
    }

#ifdef FPGA_DEBUG
  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
#endif

#ifdef FPGA_DEBUG
  printf("write configuration data into fpga\n");
#endif
  /* write configuration-data into fpga... */

  /* send 0xff 0x20 */
  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;

  /*
  ** Bit_DeCompression
  **   Code 1           .. maxOnes     : n                 '1's followed by '0'     
  **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
  **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
  **        255                        :                   '1'
  */

  for (i=index; i<size; i++)
    {
      b = fpgadata[i];
      if ((b >= 1) && (b <= MAX_ONES))
	{
	  for(bit=0; bit<b; bit++)
            {
              FPGA_WRITE_1;
            }
	  FPGA_WRITE_0;
	}
      else if (b == (MAX_ONES+1))
	{
	  for(bit=1; bit<b; bit++)
            {
              FPGA_WRITE_1;
            }
	}
      else if ((b >= (MAX_ONES+2)) && (b <= 254))
	{
	  for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
            {
              FPGA_WRITE_0;
            }
          FPGA_WRITE_1;
	}
      else if (b == 255)
        {
          FPGA_WRITE_1;
        }
    }

#ifdef FPGA_DEBUG
  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
#endif

  /*
   * Check if fpga's DONE signal - correctly booted ?
   */

  /* Setup timer */
  start = get_timer(0);
  
  /* Wait for FPGA end of programming period .  */
  while (!(in32(IBM405GP_GPIO0_IR) & FPGA_DONE))
    {
      /* Check for timeout */
      if (get_timer(start) > 3)
        {
#ifdef FPGA_DEBUG
          printf("FPGA: Booting failed!\n");
#endif
          return ERROR_FPGA_PRG_DONE;
        }
    }

#ifdef FPGA_DEBUG
  printf("FPGA: Booting successful!\n");
#endif
  return 0;
}
