/**************************************************************************
Etherboot -  BOOTP/TFTP Bootstrap Program
Skeleton NIC driver for Etherboot
***************************************************************************/

/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2, or (at
 * your option) any later version.
 */

/*
 * This file is a modified version from the Galileo polled mode
 * network driver for the ethernet contained within the GT64260
 * chip. It has been modified to fit into the ppcboot framework, from
 * the original (etherboot) setup.  Also, additional cleanup and features
 * were added.
 *
 * - Josh Huber <huber@mclx.com>
 */

#include <ppcboot.h>
#include <malloc.h>
#include <cmd_bsp.h>
#include <galileo/gt64260R.h>
#include <galileo/core.h>
#include <asm/cache.h>
#include <miiphy.h>
#include <net.h>

#include "eth.h"
#include "eth_addrtbl.h"

/* if you like verbose output, turn this on! */
#undef DEBUG

/* Restart autoneg if we detect link is up on phy init. */

/*
 * The GT doc's say that after Rst is deasserted, and the PHY
 * reports autoneg compleate, it runs through its autoneg 
 * procedures. This doesn't seem to be the case for MII
 * PHY's. To work around this check for link up && autoneg
 * compleate when initilizing the port. If they are both set,
 * then restart PHY autoneg. Of course, it may be something
 * compleatly different. 
 */
#ifdef CONFIG_ETHER_PORT_MII
# define RESTART_AUTONEG
#endif

/* do this if you want to filter for our mac */
#define USE_MAC_HASH_TABLE

/* do this if you dont want to use snooping */
#define USE_SOFTWARE_CACHE_MANAGEMENT

#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
#define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
#else
/* bummer - w/o flush, nothing works, even with snooping - FIXME */
// #define FLUSH_DCACHE(a,b)
#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
#define INVALIDATE_DCACHE(a,b)
#endif


/* locals */
static eth0_tx_desc_single *eth0_tx_desc;
static eth0_rx_desc_single *eth0_rx_desc;
static char *eth0_tx_buffer;
static char *eth0_rx_buffer[NR];

#ifdef ZUMA_NTL
/* for intel LXT972 */
static const char ether_port_phy_addr[3]={0,1,2};
#else
static const char ether_port_phy_addr[3]={4,5,6};
#endif

#define ETHER_PORT_PHY (ether_port_phy_addr[CONFIG_ETHER_PORT])

/* calculate the offset to the desired ethernet registers */
/* the registers are offset by 0x400 for each port -- see the headers */
#define REG_OFF (CONFIG_ETHER_PORT * ETHERNET_PORTS_DIFFERENCE_OFFSETS)

static inline unsigned short
miiphy_read_ret(unsigned short phy, unsigned short reg)
{
    unsigned short val;
    miiphy_read(phy,reg,&val);
    return val;
}


/**************************************************************************
RESET - Reset adapter
***************************************************************************/
void
evb64260_eth0_reset(bd_t *bis)
{
	printf ("RESET\n");
	/* put the card in its initial state */
}

static void evb64260_handle_SMI(unsigned int icr)
{
#ifdef DEBUG
    printf("SMI interrupt: ");

    if(icr&0x20000000) {
    	printf("SMI done\n");
    }
#endif

    if(icr&0x10000000) {
        unsigned int psr;
	psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
#ifdef DEBUG
	printf("PHY state change:\n"
	       "  GT:%s:%s:%s:%s\n"
		psr&1?"100":" 10",
		psr&8?" Link":"nLink",
		psr&2?"FD":"HD",
		psr&4?" FC":"nFC");

#ifdef ZUMA_NTL /* non-standard mii reg (intel lxt972a) */
	{
        unsigned short mii_11;
	mii_11=miiphy_read_ret(ETHER_PORT_PHY,0x11);

	printf(" mii:%s:%s:%s:%s %s:%s %s\n",
		mii_11&(1<<14)?"100":" 10",
		mii_11&(1<<10)?" Link":"nLink",
		mii_11&(1<<9)?"FD":"HD",
		mii_11&(1<<4)?" FC":"nFC",

		mii_11&(1<<7)?"ANc":"ANnc",
		mii_11&(1<<8)?"AN":"Manual",
		""
		);
	}
#endif /* ZUMA_NTL */
#endif /* DEBUG */
    }
}

static int
evb64260_eth0_receive(unsigned int icr)
{
	int eth_len=0;
	char *eth_data;

	eth0_rx_desc_single *rx=&eth0_rx_desc[(RDN_ETH0)];

	INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));

	if (rx->command_status & 0x80000000) {
		return 0; // No packet received
	}

	eth_len = (unsigned int)
		(rx->buff_size_byte_count) & 0x0000ffff;
	eth_data = (char *) eth0_rx_buffer[RDN_ETH0];

#ifdef DEBUG
	if (eth_len) {
		printf ("%s: Recived %d byte Packet @ 0x%p\n",
			__FUNCTION__, eth_len, eth_data);
	}
#endif
	/*
	 * packet is now in:
	 * eth0_rx_buffer[RDN_ETH0];
	 */

	/* let the upper layer handle the packet */
	NetReceive (eth_data, eth_len);

	rx->buff_size_byte_count = 1536<<16;


	/* GT96100 Owner */
	rx->command_status = 0x80000000;

	FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));

	RDN_ETH0 ++;
	if (RDN_ETH0 == NR) {RDN_ETH0 = 0;}

	sync();

	/* Start Rx*/
	GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);

#ifdef DEBUG
	{
	    int i;
	    for (i=0;i<12;i++) {
		printf(" %02x", eth_data[i]);
	    }
	}
	printf(": %d bytes\n", eth_len);
#endif
	INVALIDATE_DCACHE((unsigned int)eth_data,
		(unsigned int)eth_data+eth_len);
	return eth_len;
}

/**************************************************************************
POLL - look for an rx frame, handle other conditions
***************************************************************************/
int
evb64260_eth0_poll(void)
{
	unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + REG_OFF);

	if(icr) {
	    GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER, 0);
#ifdef DEBUG
	    printf("poll got ICR %08x\n", icr);
#endif
	    /* SMI done or PHY state change*/
	    if(icr&0x30000000) evb64260_handle_SMI(icr);  
	}
	/* always process. We aren't using RX interrupts */
	return evb64260_eth0_receive(icr);
}

/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
int
evb64260_eth0_transmit(unsigned int s, volatile char *p)
{
	unsigned int old_command_stat,old_psr;
	eth0_tx_desc_single *tx=&eth0_tx_desc[(TDN_ETH0)];

	/* wait for tx to be ready */
	INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
	while (tx->command_status & 0x80000000) {
	    int i;
	    for(i=0;i<1000;i++);
	    INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
	}
  
	GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF,
		      (unsigned int)tx);

#ifdef DEBUG
	printf("copying to tx_buffer [%p], length %x, desc = %p\n",
	       eth0_tx_buffer, s, eth0_tx_desc);
#endif
	memcpy(eth0_tx_buffer, (char *) p, s);

	tx->buff_pointer = eth0_tx_buffer;
	tx->bytecount_reserved = ((__u16)s) << 16;

	/*    31 - own
	 *    22 - gencrc
	 * 18:16 - pad, last, first */
	tx->command_status = (1<<31) | (1<<22) | (7<<16);
#if 0	
	/* FEr #18 */
	tx->next_desc = NULL;
#else
	tx->next_desc =
		(struct eth0_tx_desc_struct *)
		&eth0_tx_desc[(TDN_ETH0+1)%NT].bytecount_reserved;

	/* cpu owned */
	eth0_tx_desc[(TDN_ETH0+1)%NT].command_status = (7<<16);	/* pad, last, first */
#endif

	old_command_stat=tx->command_status,
	old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);

	FLUSH_DCACHE((unsigned int)tx,
		(unsigned int)&eth0_tx_desc[(TDN_ETH0+2)%NT]);

	FLUSH_DCACHE((unsigned int)eth0_tx_buffer,(unsigned int)eth0_tx_buffer+s);

	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x01000000);

#ifdef DEBUG
	{
	    unsigned int command_stat=0;
	    printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
	    /* wait for tx to be ready */
	    do {
		unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
		command_stat=tx->command_status;
		if(command_stat!=old_command_stat || psr !=old_psr) {
		    printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
		    old_command_stat = command_stat;
		    old_psr = psr;
		}
		// evb64260_eth0_poll();
	    } while (command_stat & 0x80000000);
      
	    printf("sent %d byte frame\n", s);

	    if((command_stat & (3<<15)) == 3) {
		printf("frame had error (stat=%08x)\n", command_stat);
	    }
	}
#endif
	return 0;
}

/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
void
evb64260_eth0_disable(void)
{
	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x80008000);
}

/**************************************************************************
MII utilities - write: write to an MII register via SMI
***************************************************************************/
int
miiphy_write(unsigned char phy, unsigned char reg,
    unsigned short data)
{
    unsigned int temp= (reg<<21) | (phy<<16) | data;

    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */

    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
    return 0;
}

/**************************************************************************
MII utilities - read: read from an MII register via SMI
***************************************************************************/
int
miiphy_read(unsigned char phy, unsigned char reg,
			unsigned short *val)
{
    unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;

    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */

    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);

    while(1) {
	temp=GTREGREAD(ETHERNET_SMI_REGISTER);
	if(temp & (1<<27)) break;		/* wait for ReadValid */
    }
    *val = temp & 0xffff;

    return 0;
}

#ifdef DEBUG
/**************************************************************************
MII utilities - dump mii registers
***************************************************************************/
static void
evb64260_dump_mii(bd_t *bis, unsigned short phy)
{
	printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
 		miiphy_read_ret(phy, 0x0),
		miiphy_read_ret(phy, 0x1),
		miiphy_read_ret(phy, 0x2),
		miiphy_read_ret(phy, 0x3)
		);
	printf("        4 - 7:   %04x %04x %04x %04x\n",
		miiphy_read_ret(phy, 0x4),
		miiphy_read_ret(phy, 0x5),
		miiphy_read_ret(phy, 0x6),
		miiphy_read_ret(phy, 0x7)
		);
	printf("        8:       %04x\n",
		miiphy_read_ret(phy, 0x8)
		);
	printf("        16-19:   %04x %04x %04x %04x\n",
		miiphy_read_ret(phy, 0x10),
		miiphy_read_ret(phy, 0x11),
		miiphy_read_ret(phy, 0x12),
		miiphy_read_ret(phy, 0x13)
		);
	printf("        20,30:   %04x %04x\n",
		miiphy_read_ret(phy, 20),
		miiphy_read_ret(phy, 30)
		);
}
#endif

#ifdef RESTART_AUTONEG

/* If link is up && autoneg compleate, and if
 * GT and PHY disagree about link capabilitys,
 * restart autoneg - something screwy with FD/HD
 * unless we do this. */
static void
check_phy_state(void)
{
	int bmsr = miiphy_read_ret(ETHER_PORT_PHY, PHY_BMSR);
	int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);

	if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
		int nego = miiphy_read_ret(ETHER_PORT_PHY, PHY_ANAR) &
				miiphy_read_ret(ETHER_PORT_PHY, PHY_ANLPAR);
		int want;

		if (nego & PHY_ANLPAR_TXFD) {
			want = 0x3;
			printf("MII: 100Base-TX, Full Duplex\n");
		} else if (nego & PHY_ANLPAR_TX) {
			want = 0x1;
			printf("MII: 100Base-TX, Half Duplex\n");
		} else if (nego & PHY_ANLPAR_10FD) {
			want = 0x2;
			printf("MII: 10Base-T, Full Duplex\n");
		} else if (nego & PHY_ANLPAR_10) {
			want = 0x0;
			printf("MII: 10Base-T, Half Duplex\n");
		} else {
			printf("MII: Unknown link-foo! %x\n", nego);
			return;
		}

		if ((psr & 0x3) != want) {
			printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
					psr & 0x3, want);
			miiphy_write(ETHER_PORT_PHY,0,
					miiphy_read_ret(ETHER_PORT_PHY,0) | (1<<9));
			udelay(10000);	/* the EVB's GT takes a while to notice phy
					   went down and up */
		}
	}
}
#endif

/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
int
evb64260_eth0_probe(bd_t *bis)
{
	static int initted=0;

	unsigned long temp;
	int i;

	if(initted) {
	    GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);
	    return 0;
	}

	initted=1;

#ifdef DEBUG
	printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
		GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
		GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
#endif

	// clear MIB counters
	for(i=0;i<255; i++)
	    temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + REG_OFF +i);

#ifdef ZUMA_NTL
	/* for intel LXT972 */

	/* led 1: 0x1=txact
	   led 2: 0xc=link/rxact
	   led 3: 0x2=rxact (N/C)
	   strch: 0,2=30 ms, enable */
	miiphy_write(ETHER_PORT_PHY, 20, 0x1c22);

	/* 2.7ns port rise time */
	//miiphy_write(ETHER_PORT_PHY, 30, 0x0<<10);
#else	
	/* already set up in mpsc.c */
	//GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);	/* b400 */
	
	/* already set up in sdram_init.S... */
	/* MPSC0, MPSC1, RMII */
	//GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);		/* f010 */
#endif
	GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
	     ether_port_phy_addr[0]     |
	    (ether_port_phy_addr[1]<<5) |
	    (ether_port_phy_addr[2]<<10));			/* 2000 */

	/* 13:12 -   10: 4x64bit burst	(cache line size = 32 bytes)
	 *    9  -    1: RIFB - interrupt on frame boundaries only
	 *  6:7  -   00: big endian rx and tx
	 *  5:2  - 1111: 15 retries */
	GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + REG_OFF,
		(2<<12) | (1<<9) | (0xf<<2) );			/* 2440 */

#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
	/* enable rx/tx desc/buffer cache snoop */
	GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20,
		&temp);						/* f200 */
	temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
	GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20,
		temp);
#endif

	/* 31  28 27  24 23  20 19  16
	 *  0000   0000   0000   0000 	[0004]
	 * 15  12 11  8   7  4   3  0
	 *  1000   1101   0000   0000	[4d00]
	 *    20 - 0=MII 1=RMII
	 *    19 - 0=speed autoneg
	 * 15:14 - framesize 1536
	 *    11 - no force link pass
	 *    10 - 1=disable fctl autoneg
	 *     8 - override prio ?? */
	temp = 0x00004d00;
#ifndef CONFIG_ETHER_PORT_MII
	temp |= (1<<20);	// RMII
#endif
	/* set En */
	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + REG_OFF,	
		     temp);				/* 2408 */

	/* hardcode E1 also? */
	/* -- according to dox, this is safer due to extra pulldowns? */
	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + 1 * 0x400,	
		     temp);				/* 2408 */

	/* wake up MAC */				 /* 2400 */
	GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, &temp);
	temp |= (1<<7);		/* enable port */
#ifdef USE_MAC_HASH_TABLE
	temp |= (1<<12);	/* hash size 1/2k */
#else
	temp |= 1;		/* promisc */
#endif
	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, temp);
							/* 2400 */

#ifdef RESTART_AUTONEG
	check_phy_state();
#endif

	printf("Waiting for link up..\n");
	/* wait for link back up */
	while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF) & 8)){
	    udelay(10);
	}
	printf("OK!\n");

	/* we're dealing with the first ethernet only for this stripped down
	 * driver */
	TDN_ETH0=0;
	RDN_ETH0=0;

	eth0_tx_desc =
		(eth0_tx_desc_single *)
		(((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
					(NT+1)) & 0xfffffff0) + 0x10);
	eth0_rx_desc =
		(eth0_rx_desc_single *)
		(((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
					(NR+1)) & 0xfffffff0) + 0x10);
	eth0_tx_buffer =
		(char *) (((unsigned int) malloc(1536) & 0xfffffff0) + 0x10);

	for (temp = 0 ; temp < NR ; temp ++) {
		eth0_rx_buffer[temp] =
			(char *)
			(((unsigned int) malloc(1536) & 0xfffffff0) + 0x10);
	}

	eth0_tx_desc[(TDN_ETH0)].command_status = 0;

	// Initialize Rx Side
	for (temp = 0; temp < NR; temp++) {
		eth0_rx_desc[temp].buff_pointer = eth0_rx_buffer[temp];
		eth0_rx_desc[temp].buff_size_byte_count = 1536<<16;

		/* GT96100 Owner */
		eth0_rx_desc[temp].command_status = 0x80000000;
		eth0_rx_desc[temp].next_desc =
			(struct eth0_rx_desc_struct *)
			&eth0_rx_desc[(temp+1)%NR].buff_size_byte_count;
	}

	FLUSH_DCACHE((unsigned int)&eth0_tx_desc[0],
		     (unsigned int)&eth0_tx_desc[NR]);
	FLUSH_DCACHE((unsigned int)&eth0_rx_desc[0],
		     (unsigned int)&eth0_rx_desc[NR]);
  
	GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF,
		      (unsigned int) eth0_tx_desc);
	GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF,
		      (unsigned int) eth0_rx_desc);
	GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + REG_OFF,
		      (unsigned int) eth0_rx_desc);

#ifdef DEBUG
	printf ("\nRx descriptor pointer is %08x %08x\n",
		GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF),
		GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + REG_OFF));
	printf ("\n\n%08x %08x\n",
		(unsigned int)eth0_rx_desc,eth0_rx_desc[0].command_status);

	printf ("Descriptor dump:\n");
	printf ("cmd status: %08x\n",eth0_rx_desc[0].command_status);
	printf ("byte_count: %08x\n",eth0_rx_desc[0].buff_size_byte_count);
	printf ("buff_ptr: %08x\n",(unsigned int)eth0_rx_desc[0].buff_pointer);
	printf ("next_desc: %08x\n\n",(unsigned int)eth0_rx_desc[0].next_desc);
	printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x0));
	printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x4));
	printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x8));
	printf ("%08x\n\n",
		*(unsigned int *) ((unsigned int)eth0_rx_desc + 0xc));
#endif

#ifdef DEBUG
	evb64260_dump_mii(bis,ETHER_PORT_PHY);
#endif

#ifdef USE_MAC_HASH_TABLE
	{
	    u8 *b=bis->bi_enetaddr;
	    u32 macH= (b[0]<<8) | b[1];
	    u32 macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];

	    /* mode 0, size 0x800 */
	    unsigned int hashtable_base =initAddressTable(CONFIG_ETHER_PORT,0,1);

	    if(!hashtable_base) {
		printf("initAddressTable failed\n");
		return -1;
	    }

	    addAddressTableEntry(CONFIG_ETHER_PORT, macH, macL, 1, 0);
	    GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + REG_OFF,
		    hashtable_base);
	}
#endif

	/* Start Rx*/
	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);
	return 0;
}
