/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * evb64260.c - main board support/init for the Galileo Eval board.
 */

#include <ppcboot.h>
#include <74xx_7xx.h>
#include <galileo/memory.h>
#include <galileo/pci.h>
#include <galileo/gt64260R.h>
#include <net.h>

#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
#include "64260.h"

#undef	DEBUG
#define	MAP_PCI

#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif

/* ------------------------------------------------------------------------- */

/* this is the GT register space location where we want it to be */
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;

/* ------------------------------------------------------------------------- */

/*
 * This is a version of the GT register space remapping function that
 * doesn't touch globals (meaning, it's ok to run from flash.)
 */

void
my_remap_gt_regs(u32 cur_loc, u32 new_loc)
{
	u32 temp;

	/* check and see if it's already moved */
	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
	if ((temp & 0xffff) == new_loc >> 20)
		return;

	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
		0xffff0000) | (new_loc >> 20);

	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);

	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
}

/*
 * board_pre_init.
 *
 * set up gal. device mappings, etc.
 */
int
board_pre_init(void)
{
	ulong tmp;
	uchar sram_boot = 0;
	cpu_t cpu = get_cpu_type();

	/*
	 * set up the GT the way the kernel wants it
	 * the call to move the GT register space will obviously
	 * fail if it has already been done, but we're going to assume
	 * that if it's not at the power-on location, it's where we put
	 * it last time. (huber)
	 */
	my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);

	/* mask all external interrupt sources */
	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
	GT_REG_WRITE(CPU_INT_0_MASK, 0);
	GT_REG_WRITE(CPU_INT_1_MASK, 0);
	GT_REG_WRITE(CPU_INT_2_MASK, 0);
	GT_REG_WRITE(CPU_INT_3_MASK, 0);

	/* now, onto the configuration */
	GT_REG_WRITE(SDRAM_CONFIGURATION, 0xd8e10200);

	/* ----- DEVICE BUS SETTINGS ------ */

        /*
         * 0 - SRAM
         * 1 - RTC
         * 2 - UART
         * 3 - Flash
         * boot - BootCS
         */

	/*
	 * the dual 7450 module requires burst access to the boot
	 * device, so the serial rom copies the boot device to the
	 * on-board sram on the eval board, and updates the correct
	 * registers to boot from the sram. (device0)
	 */
	if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE)
		sram_boot = 1;

	if (!sram_boot)
		memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE);
	memoryMapDevice1Space(CFG_DEV1_SPACE, CFG_DEV1_SIZE);
	memoryMapDevice2Space(CFG_DEV2_SPACE, CFG_DEV2_SIZE);
	memoryMapDevice3Space(CFG_DEV3_SPACE, CFG_DEV3_SIZE);

	/* configure device timing */
	if (!sram_boot)
		GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);

	/* detect if we are booting from the 32 bit flash */
	if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
		/* 32 bit boot flash */
		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
	} else {
		/* 8 bit boot flash */
		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
	}

	/* cpu configuration register */
	tmp = GTREGREAD(CPU_CONFIGURATION);

	/* set the AACK delay bit
	 * see Res#14 */
	tmp |= CPU_CONF_AACK_DELAY;

	if (cpu == CPU_750CX) {
		tmp |= CPU_CONF_DP_VALID;
		tmp &= ~CPU_CONF_AP_VALID;
	} else {
		tmp |= CPU_CONF_DP_VALID;
		tmp |= CPU_CONF_AP_VALID;
	}

	/* this only works with the MPX bus */
	tmp &= ~CPU_CONF_RD_OOO;
	tmp &= ~CPU_CONF_PIPELINE;
	tmp |= CPU_CONF_TA_DELAY;

	GT_REG_WRITE(CPU_CONFIGURATION, tmp);

	/* CPU master control register */
	tmp = GTREGREAD(CPU_MASTER_CONTROL);

	tmp |= CPU_MAST_CTL_ARB_EN;

	if ((cpu == CPU_7400) ||
	    (cpu == CPU_7410) ||
	    (cpu == CPU_7450)) {

		tmp |= CPU_MAST_CTL_CLEAN_BLK;
		tmp |= CPU_MAST_CTL_FLUSH_BLK;

	} else {
		/* cleanblock must be cleared for CPUs
		 * that do not support this command
		 * see Res#1 */
		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
	}

	GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);

	/* PCI interface settings */
	GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
	GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
	GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
	GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);

	/* MPP setup */
	GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
	GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
	GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
	GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);

	/* XXX */
	GT_REG_WRITE(GPP_LEVEL_CONTROL, 0x000002c6);
	GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x00000102);

	return 0;
}

/* various things to do after relocation */

void
misc_init_r(bd_t *bd)
{
#ifdef CONFIG_MPSC
	mpsc_init2();
#endif

#if 0
	/* disable the dcache and MMU */
	dcache_lock();
//	disable_addr_trans();
//	invalidate_bats();
//	dcache_disable();
#endif
}

void
after_reloc(bd_t *bd, ulong dest_addr)
{
	/* check to see if we booted from the sram.  If so, move things
	 * back to the way they should be. (we're running from main
	 * memory at this point now */

	if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
		memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE);
		memoryMapDeviceBootSpace(CFG_FLASH_BASE, _1M);
	}

	/* now, jump to the main ppcboot board init code */
	board_init_r(bd, dest_addr);

	/* NOTREACHED */
}

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 *
 * right now, assume borad type. (there is just one...after all)
 */

int
checkboard (void)
{
	int l_type = 0;

	printf ("EVB64260\n");

	return (l_type);
}

/* utility functions */

void
debug_led(int led, int mode)
{
        volatile int *addr;
        int dummy;

        if (mode == 1) {
                switch (led) {
                case 0:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
                        break;

                case 1:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
                        break;

                case 2:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
                        break;
                }
        } else if (mode == 0) {
                switch (led) {
                case 0:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
                        break;

                case 1:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
                        break;

                case 2:
                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
                        break;
                }
        }

        dummy = *addr;
}

#if (CONFIG_COMMANDS & CFG_CMD_NET)

/* 
 * ethernet handlers.  mostly just pass off to routines in
 * eth.c
 */

int
eth_init(bd_t *bis)
{
	static short init_done = 0;

	if (!init_done) {
		init_done = 1;
		return evb64260_eth0_probe(bis);
	}

	return 0;
}

int
eth_send(volatile void *packet, int length)
{
#ifdef DEBUG
	printf ("%s: %d byte packet @ 0x%p\n", __FUNCTION__, length, packet);
#endif
	return evb64260_eth0_transmit(length, packet);
}

int
eth_rx(void)
{
	return evb64260_eth0_poll();
}

void
eth_halt(void)
{
	evb64260_eth0_disable();
}

#endif	/* CFG_CMD_NET */

/* we're not using this right now...btw, it was lifted from the
 * galileo code in Dink32 [josh] */

#if 0

void
display_mem_map(void)
{
	unsigned int base,size,width;
	/* SDRAM */
	printf("SDRAM\n");
	base = memoryGetBankBaseAddress(BANK0);
	size = memoryGetBankSize(BANK0);
	if(size !=0)
	{
		printf("BANK0: base - 0x%x\tsize - %d bytes\n",base,size);
	}
	base = memoryGetBankBaseAddress(BANK1);
	size = memoryGetBankSize(BANK1);
	if(size !=0)
	{
		printf("BANK1: base - 0x%x\tsize - %d bytes\n",base,size);
	}
	base = memoryGetBankBaseAddress(BANK2);
	size = memoryGetBankSize(BANK2);
	if(size !=0)
	{
		printf("BANK2: base - 0x%x\tsize - %d bytes\n",base,size);
	}
	base = memoryGetBankBaseAddress(BANK3);
	size = memoryGetBankSize(BANK3);
	if(size !=0)
	{
		printf("BANK3: base - 0x%x\tsize - %d bytes\n",base,size);
	}
	/* Devices */
	printf("\nDEVICES\n");
	base = memoryGetDeviceBaseAddress(DEVICE0); /* SRAM */
	size = memoryGetDeviceSize(DEVICE0);
	width= memoryGetDeviceWidth(DEVICE0) * 8;
	printf("SRAM:  base - 0x%x\tsize - %d bytes\twidth - %d bits\n",
	       base, size, width);
	base = memoryGetDeviceBaseAddress(DEVICE1); /* RTC */
	size = memoryGetDeviceSize(DEVICE1);
	width= memoryGetDeviceWidth(DEVICE1) * 8;
	printf("RTC:   base - 0x%x\tsize - %d bytes\twidth - %d bits\n",
	       base, size, width);
	base = memoryGetDeviceBaseAddress(DEVICE2); /* UART */
	size = memoryGetDeviceSize(DEVICE2);
	width= memoryGetDeviceWidth(DEVICE2) * 8;
	printf("UART:  base - 0x%x\tsize - %d bytes\twidth - %d bits\n",
	       base, size, width);
	base = memoryGetDeviceBaseAddress(DEVICE3); /* Flash */
	size = memoryGetDeviceSize(DEVICE3);
	width= memoryGetDeviceWidth(DEVICE3) * 8;
	printf("FLASH: base - 0x%x\tsize - %d bytes\twidth - %d bits\n",
	       base, size, width);
	base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
	size = memoryGetDeviceSize(BOOT_DEVICE);
	width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
	printf("BOOT:  base - 0x%x\tsize - %d bytes\twidth - %d bits\n",
	       base, size, width);
	/* CPU's PCI windows */
	printf("\nCPU's PCI 0 windows\n");
	base = pci0GetMemory0Base();
	size = pci0GetMemory0Size();
	printf("MEMORY 0: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci0GetMemory1Base();
	size = pci0GetMemory1Size();
	printf("MEMORY 1: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci0GetMemory2Base();
	size = pci0GetMemory2Size();
	printf("MEMORY 2: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci0GetMemory3Base();
	size = pci0GetMemory3Size();
	printf("MEMORY 3: base - 0x%x\tsize - %d bytes\n",base,size);
    
	printf("\nCPU's PCI 1 windows\n");
	base = pci1GetMemory0Base();
	size = pci1GetMemory0Size();
	printf("MEMORY 0: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci1GetMemory1Base();
	size = pci1GetMemory1Size();
	printf("MEMORY 1: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci1GetMemory2Base();
	size = pci1GetMemory2Size();
	printf("MEMORY 2: base - 0x%x\tsize - %d bytes\n",base,size);
	base = pci1GetMemory3Base();
	size = pci1GetMemory3Size();
	printf("MEMORY 3: base - 0x%x\tsize - %d bytes\n",base,size);
}

#endif
