 /*
 * (C) Copyright 2001
 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */
#ifndef _PCI_PARTS_H_
#define _PCI_PARTS_H_


/* Board specific file containing:
 * - PCI Memory Mapping
 * - PCI IO Mapping
 * - PCI Interrupt Mapping
 */

/* PIP405 PCI INT Routing:
 *                      IRQ0  VECTOR
 * PIXX4 IDSEL  = AD16  INTA#  28 (Function 2 USB is INTD# = 31)
 * VGA   IDSEL  = AD17  INTB#  29
 * SCSI  IDSEL  = AD18  INTC#  30
 * PC104 IDSEL0 = AD20  INTA#  28
 * PC104 IDSEL1 = AD21  INTB#  29
 * PC104 IDSEL2 = AD22  INTC#  30
 * PC104 IDSEL3 = AD23  INTD#  31
 *
 * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
 *              ^         ^         ^     ^   ^
 *             31        23        15    10   7
 * E = Enabled
 * B = Bussnumber
 * D = Devicenumber (Device0 = AD10)
 * F = Functionnumber
 * R = Registernumber
 *
 * Device = (busdevfunc>>11) + 10
 * Vector = devicenumber % 4 + 28
 *
 */
#define PCI_DEV_NUMBER(x)	(((x>>11) & 0x1f) + 10)
#define PCI_IRQ_VECTOR(x)	(PCI_DEV_NUMBER(x) % 4) + 28


/* PCI Device List for PIP405 */

/* Mapping:
 * +-------------+------------+------------+--------------------------------+
 * ¦ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function              |
 * +-------------+------------+------------+--------------------------------+
 * |  0x00000000 |            | 0xA0000000 | ISA Memory (hard wired)        |
 * |  0x00FFFFFF |            | 0xA0FFFFFF |                                |
 * +-------------+------------+------------+--------------------------------+
 * |             | 0x00000000 | 0xE8000000 | ISA IO (hard wired)            |
 * |             | 0x0000FFFF | 0xE800FFFF |                                |
 * +-------------+------------+------------+--------------------------------+
 * |  0x80000000 |            | 0x80000000 | VGA Controller Memory          |
 * |  0x80FFFFFF |            | 0x80FFFFFF |                                |
 * +-------------+------------+------------+--------------------------------+
 * |  0x81000000 |            | 0x81000000 | SCSI Controller Memory         |
 * |  0x81FFFFFF |            | 0x81FFFFFF |                                |
 * +-------------+------------+------------+--------------------------------+
 */

static PCI_DEV_CFG_TABLE pcidevtbl[]={
/* PIIX4 ISA Bridge Function 0 */
{0x8086,0x7110,	0xff,0, {
	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1},/* enable Continous SERIRQ Pin */
	{PCI_CFG_PIIX4_GENCFG,	0x00010000,	4},/* enable SERIRQs	 */
	{PCI_CFG_PIIX4_XBCS,	0x0080,		2}, /* disable all peri CS  */
	{PCI_CFG_PIIX4_RTCCFG,  0x21,		1}, /* enable RTC	   */
	{0xFFFF, 0,0}}				/* end of device table */
},
/* PIIX4 IDE Controller Function 1 */
{0x8086,0x7111,0xff,1,{
	{PCI_CFG_COMMAND,      0x0001,     2},/* enable IO access */
	{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4},/* enable Both IDE channels	 */
	{0xFFFF, 0,0}}				/* end of device table */
},
/* PIIX4 USB Controller Function 2 */
{0x8086,0x7112,0xff,2,{
	{PCI_CFG_DEV_INT_LINE,            31, 1},/* Int vector = 31 */
	{PCI_CFG_BASE_ADDRESS_4,  0x0000E001, 4},/* Set IO Address to 0xe000 to 0xe01F	 */
	{PCI_CFG_LATENCY_TIMER,         0x80, 1},/* Latency Timer 0x80 */
	{0xC0,						  0x2000, 2}, /* Legacy support */
	{PCI_CFG_COMMAND,             0x0005, 2},/* enable IO access and Master */
	{0xFFFF, 0,0}}				/* end of device table */
},
/* VGA Controller  ct69000 (logical device 0) */
{0x102C,0x00C0,0xff,0,{
	{PCI_CFG_BASE_ADDRESS_0, 0x80000000, 4},/* Frame buffer access */
	{PCI_CFG_EXPANSION_ROM,  0x00000000, 4},/* disable ROM */
	{PCI_CFG_DEV_INT_LINE,           29, 1},/* Int vector = 29 */
	{PCI_CFG_COMMAND,            0x0003, 2},/* enable IO access */
	{0xFFFF, 0,0}}				/* end of device table */
},
/* Symbois 810 function 0 */
{0x1000,0x0001,0xff,0,{
	{PCI_CFG_BASE_ADDRESS_0, 0x00001001, 4},/* IO Base address */
	{PCI_CFG_BASE_ADDRESS_1, 0x81000000, 4},/* Memory Base address */
	{PCI_CFG_DEV_INT_LINE,           30, 1},/* Int vector = 30 */
	{PCI_CFG_COMMAND,            0x0006, 2},/* enable Memory access and busmaster */
	{0xFFFF, 0,0}}				/* end of device table */
},
/* Terminator */
{0xffff,0xffff,0xff,0xff,{
	{0xFFFF, 0,0}}				/* end of device table */
}
};
#endif /* _PCI_PARTS_H_ */





