/* PCI.h - PCI functions header file */
  
/* Copyright - Galileo technology. */

#ifndef __INCpcih
#define __INCpcih

/* includes */

#include"core.h"

/* Macros */

/* The next Macros configurate the initiator board (SELF) or any any agent on
   the PCI to become: MASTER, response to MEMORY transactions , response to
   IO transactions or TWO both MEMORY_IO transactions. Those configuration
   are for both PCI0 and PCI1. */
#define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg(                  \
          PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )
          
#define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg(                 \
          PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg(                  \
          PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )
          
#define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg(                 \
          PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg(                  \
          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )           

#define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg(                  \
          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg(                      \
          PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg(                      \
          PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg(                   \
          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg(                   \
          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )

#define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg(                        \
          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \
          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg(                        \
          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \
          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define 	MASTER_ENABLE			BIT2  
#define		MEMORY_ENABLE			BIT1  
#define		I_O_ENABLE  			BIT0  
#define     SELF                    32 
/* Agent on the PCI bus may have up to 6 BARS. */
#define     BAR0                    0x10
#define     BAR1                    0x14
#define     BAR2                    0x18
#define     BAR3                    0x1c
#define     BAR4                    0x20
#define     BAR5                    0x24

/* Defines for the access regions. */
#define     PREFETCH_ENABLE                 BIT12
#define     PREFETCH_DISABLE                NO_BIT
#define     DELAYED_READ_ENABLE             BIT13
#define     CACHING_ENABLE                  BIT14
/* aggresive prefetch: PCI slave prefetch two burst in advance*/
#define     AGGRESIVE_PREFETCH              BIT16 
/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
#define     READ_LINE_AGGRESSIVE_PREFETCH   BIT17
/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
#define     READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
#define     MAX_BURST_4                     NO_BIT
#define     MAX_BURST_8                     BIT20  /* Bits[21:20] = 01 */
#define     MAX_BURST_16                    BIT21  /* Bits[21:20] = 10 */
#define     PCI_BYTE_SWAP                   NO_BIT /* Bits[25:24] = 00 */
#define     PCI_NO_SWAP                     BIT24  /* Bits[25:24] = 01 */
#define     PCI_BYTE_AND_WORD_SWAP          BIT25  /* Bits[25:24] = 10 */
#define     PCI_WORD_SWAP                   BIT24 | BIT25 /* Bits[25:24] = 11 */
#define     PCI_ACCESS_PROTECT              BIT28
#define     PCI_WRITE_PROTECT               BIT29

/* typedefs */

typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
                                REGION6,REGION7} PCI_ACCESS_REGIONS;

typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;

typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} 
                            PCI_SNOOP_TYPE;
typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
                              PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} 
                              PCI_SNOOP_REGION;

typedef struct pciDevice
{
    char            type[20];
    unsigned int    deviceNum;
    unsigned int    venID;                                            
    unsigned int    deviceID;
    unsigned int    bar0Base;
    unsigned int    bar0Size;
    unsigned int    bar0Type;
    unsigned int    bar1Base;
    unsigned int    bar1Size;
    unsigned int    bar1Type;
    unsigned int    bar2Base;
    unsigned int    bar2Size;
    unsigned int    bar2Type;
    unsigned int    bar3Base;
    unsigned int    bar3Size;
    unsigned int    bar3Type;
    unsigned int    bar4Base;
    unsigned int    bar4Size;
    unsigned int    bar4Type;
    unsigned int    bar5Base;
    unsigned int    bar5Size;
    unsigned int    bar5Type;
} PCI_DEVICE;

typedef struct pciSelfBars
{
    unsigned int    SCS0Base;
    unsigned int    SCS0Size;
    unsigned int    SCS1Base;
    unsigned int    SCS1Size;
    unsigned int    SCS2Base;
    unsigned int    SCS2Size;
    unsigned int    SCS3Base;
    unsigned int    SCS3Size;
    unsigned int    internalMemBase;
    unsigned int    internalIOBase;
    unsigned int    CS0Base;
    unsigned int    CS0Size;
    unsigned int    CS1Base;
    unsigned int    CS1Size;
    unsigned int    CS2Base;
    unsigned int    CS2Size;
    unsigned int    CS3Base;
    unsigned int    CS3Size;
    unsigned int    CSBootBase;
    unsigned int    CSBootSize;
    unsigned int    P2PMem0Base;
    unsigned int    P2PMem0Size;
    unsigned int    P2PMem1Base;
    unsigned int    P2PMem1Size;
    unsigned int    P2PIOBase;
    unsigned int    P2PIOSize;
    unsigned int    CPUBase;
    unsigned int    CPUSize;
} PCI_SELF_BARS;
/* read/write configuration registers on local PCI bus. */
void pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
                           unsigned int data);
void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
                           unsigned int data);
unsigned int pci0ReadConfigReg (unsigned int regOffset,
                                   unsigned int pciDevNum);
unsigned int pci1ReadConfigReg (unsigned int regOffset,
                                   unsigned int pciDevNum);
/* read/write configuration registers on another PCI bus. */
void pci0OverBridgeWriteConfigReg(unsigned int regOffset,
                                     unsigned int pciDevNum,
                                     unsigned int busNum,unsigned int data);
void pci1OverBridgeWriteConfigReg(unsigned int regOffset,
                                     unsigned int pciDevNum,
                                     unsigned int busNum,unsigned int data);
unsigned int pci0OverBridgeReadConfigReg(unsigned int regOffset,
                                            unsigned int pciDevNum,
                                            unsigned int busNum);
unsigned int pci1OverBridgeReadConfigReg(unsigned int regOffset,
                                            unsigned int pciDevNum,
                                            unsigned int busNum);
/* Performs full scane on both PCI and returns all detail possible on the 
   agents which exist on the bus. */
void pci0ScanDevices(PCI_DEVICE *pci0Detect,unsigned int numberOfElment);
void pci1ScanDevices(PCI_DEVICE *pci1Detect,unsigned int numberOfElment);

/*      Master`s memory space   */

void pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength);
void pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength);
void pci0MapMemory0space(unsigned int pci0Mem0Base,
                         unsigned int pci0Mem0Length);
void pci1MapMemory0space(unsigned int pci1Mem0Base,
                         unsigned int pci1Mem0Length);
void pci0MapMemory1space(unsigned int pci0Mem1Base,
                         unsigned int pci0Mem1Length);
void pci1MapMemory1space(unsigned int pci1Mem1Base,
                         unsigned int pci1Mem1Length);
void pci0MapMemory2space(unsigned int pci0Mem2Base,
                         unsigned int pci0Mem2Length);
void pci1MapMemory2space(unsigned int pci1Mem2Base,
                         unsigned int pci1Mem2Length);
void pci0MapMemory3space(unsigned int pci0Mem3Base,
                         unsigned int pci0Mem3Length);
void pci1MapMemory3space(unsigned int pci1Mem3Base,
                         unsigned int pci1Mem3Length);

unsigned int pci0GetIOspaceBase(void);
unsigned int pci0GetIOspaceSize(void);
unsigned int pci0GetMemory0Base(void);
unsigned int pci0GetMemory0Size(void);
unsigned int pci0GetMemory1Base(void);
unsigned int pci0GetMemory1Size(void);
unsigned int pci0GetMemory2Base(void);
unsigned int pci0GetMemory2Size(void);
unsigned int pci0GetMemory3Base(void);
unsigned int pci0GetMemory3Size(void);

unsigned int pci1GetIOspaceBase(void);
unsigned int pci1GetIOspaceSize(void);
unsigned int pci1GetMemory0Base(void);
unsigned int pci1GetMemory0Size(void);
unsigned int pci1GetMemory1Base(void);
unsigned int pci1GetMemory1Size(void);
unsigned int pci1GetMemory2Base(void);
unsigned int pci1GetMemory2Size(void);
unsigned int pci1GetMemory3Base(void);
unsigned int pci1GetMemory3Size(void);

/*      Slave`s memory space   */

void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
void pci0MapMemoryBank0(unsigned int pci0Dram0Base,
                        unsigned int pci0Dram0Size);
void pci1MapMemoryBank0(unsigned int pci1Dram0Base,
                        unsigned int pci1Dram0Size);
void pci0MapMemoryBank1(unsigned int pci0Dram1Base,
                        unsigned int pci0Dram1Size);
void pci1MapMemoryBank1(unsigned int pci1Dram1Base,
                        unsigned int pci1Dram1Size);
void pci0MapMemoryBank2(unsigned int pci0Dram2Base,
                        unsigned int pci0Dram2Size);
void pci1MapMemoryBank2(unsigned int pci1Dram2Base,
                        unsigned int pci1Dram2Size);
void pci0MapMemoryBank3(unsigned int pci0Dram3Base,
                        unsigned int pci0Dram3Size);
void pci1MapMemoryBank3(unsigned int pci1Dram3Base,
                        unsigned int pci1Dram3Size);
void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
                               unsigned int pci0Dev0Length);
void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
                               unsigned int pci1Dev0Length);
void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
                               unsigned int pci0Dev1Length);
void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
                               unsigned int pci1Dev1Length);
void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
                               unsigned int pci0Dev2Length);
void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
                               unsigned int pci1Dev2Length);
void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
                               unsigned int pci0Dev3Length);
void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
                               unsigned int pci1Dev3Length);
void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
                                  unsigned int pci0DevBootLength);
void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
                                  unsigned int pci1DevBootLength);
void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, 
                         unsigned int pci0P2pMem0Length);
void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, 
                         unsigned int pci1P2pMem0Length);
void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, 
                         unsigned int pci0P2pMem1Length);
void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, 
                         unsigned int pci1P2pMem1Length);
void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, 
                       unsigned int pci0P2pIoLength);
void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, 
                       unsigned int pci1P2pIoLength);

void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);

bool  pci0SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, 
                            unsigned int baseAddress,unsigned int regionLength);

bool  pci1SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, 
                            unsigned int baseAddress,unsigned int regionLength);
void  pci0DisableAccessRegion(PCI_ACCESS_REGIONS region);
void  pci1DisableAccessRegion(PCI_ACCESS_REGIONS region);

/* PCI arbiter */

bool pci0ArbiterEnable(void);
bool pci1ArbiterEnable(void);
bool pci0ArbiterDisable(void);
bool pci1ArbiterDisable(void);
bool pci0SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent,
                                  PCI_AGENT_PRIO externalAgent0,
                                  PCI_AGENT_PRIO externalAgent1,
                                  PCI_AGENT_PRIO externalAgent2,
                                  PCI_AGENT_PRIO externalAgent3,
                                  PCI_AGENT_PRIO externalAgent4,
                                  PCI_AGENT_PRIO externalAgent5);
bool pci1SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent,
                                  PCI_AGENT_PRIO externalAgent0,
                                  PCI_AGENT_PRIO externalAgent1,
                                  PCI_AGENT_PRIO externalAgent2,
                                  PCI_AGENT_PRIO externalAgent3,
                                  PCI_AGENT_PRIO externalAgent4,
                                  PCI_AGENT_PRIO externalAgent5);
bool pci0ParkingDisable(PCI_AGENT_PARK internalAgent,
                        PCI_AGENT_PARK externalAgent0,
                        PCI_AGENT_PARK externalAgent1,
                        PCI_AGENT_PARK externalAgent2,
                        PCI_AGENT_PARK externalAgent3,
                        PCI_AGENT_PARK externalAgent4,
                        PCI_AGENT_PARK externalAgent5);
bool pci1ParkingDisable(PCI_AGENT_PARK internalAgent,
                        PCI_AGENT_PARK externalAgent0,
                        PCI_AGENT_PARK externalAgent1,
                        PCI_AGENT_PARK externalAgent2,
                        PCI_AGENT_PARK externalAgent3,
                        PCI_AGENT_PARK externalAgent4,
                        PCI_AGENT_PARK externalAgent5);
bool pci0EnableBrokenAgentDetection(unsigned char brokenValue);
bool pci1EnableBrokenAgentDetection(unsigned char brokenValue);
bool pci0DisableBrokenAgentDetection(void);
bool pci1DisableBrokenAgentDetection(void);

/* PCI-to-PCI (P2P) */

bool pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,
                   unsigned int busNum,unsigned int devNum);
bool pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,
                   unsigned int busNum,unsigned int devNum);
/* PCI Cache-coherency */

bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType,
                            unsigned int baseAddress,
                            unsigned int regionLength);
bool pci1SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType,
                            unsigned int baseAddress,
                            unsigned int regionLength);
#endif /* __INCpcih */
