/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
#include <cmd_bsp.h>

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

/*
 * 66 MHz SDRAM access using UPM A
 */
const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
         * This is no UPM entry point. The following definition uses
         * the remaining space to establish an initialization
         * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 */

int checkboard (void)
{
	printf ("Litronic Monitor IV\n");
	return (1);
}

/* ------------------------------------------------------------------------- */

long int
initdram (int board_type)
{
    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immr->im_memctl;
    long int size_b0;
    int i;

    /*
     * Configure UPMA for SDRAM
     */
    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

    memctl->memc_mptpr = CFG_MPTPR;

    /* burst length=4, burst type=sequential, CAS latency=2 */
    memctl->memc_mar = 0x00000088;

    /*
     * Map controller bank 3 to the SDRAM bank at preliminary address.
     */
    memctl->memc_or3 = CFG_OR3_PRELIM;
    memctl->memc_br3 = CFG_BR3_PRELIM;

    /* initialize memory address register */
    memctl->memc_mamr = CFG_MAMR;	/* refresh not enabled yet */

    /* mode initialization (offset 5) */
    udelay(200);	/* 0x80006105 */
    memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);

    /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
    udelay(1);		/* 0x80006130 */
    memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
    udelay(1);		/* 0x80006130 */
    memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);

    udelay(1);		/* 0x80006106 */
    memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);

    memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */

    udelay(200);

    /* Need at least 10 DRAM accesses to stabilize */
    for (i=0; i<10; ++i) {
	volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE3_PRELIM;
	unsigned long val;

	val = *(addr + i);
	*(addr + i) = val;
    }

    /*
     * Check Bank 0 Memory Size for re-configuration
     */
    size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

    memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;

    /*
     * Final mapping:
     */

    memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | \
    				OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
    memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
    udelay(1000);

    return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immr->im_memctl;
    volatile long int	 *addr;
    ulong		  cnt, val;
    ulong		  save[32];	/* to make test non-destructive */
    unsigned char	  i = 0;

    memctl->memc_mamr = mamr_value;

    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
	addr = base + cnt;	/* pointer arith! */

	save[i++] = *addr;
	*addr = ~cnt;
    }

    /* write 0 to base address */
    addr = base;
    save[i] = *addr;
    *addr = 0;

    /* check at base address */
    if ((val = *addr) != 0) {
	*addr = save[i];
	return (0);
    }

    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
	addr = base + cnt;	/* pointer arith! */

	val = *addr;
	*addr = save[--i];

	if (val != (~cnt)) {
	    return (cnt * sizeof(long));
	}
    }
    return (maxsize);
}

/* ------------------------------------------------------------------------- */

#ifndef	PB_ENET_TENA
# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
#endif

int board_pre_init (void)
{
	volatile immap_t     *immr  = (immap_t *)CFG_IMMR;

	/* Disable Ethernet TENA on Port B
	 * Necessary because of pull up in COM3 port.
	 *
         * This is just a preliminary fix, intended to turn off TENA
         * as soon as possible to avoid noise on the network. Once
         * I²C is running we will make sure the interface is
         * correctly initialized.
	 */
	immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;
	immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
	immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA;		/* set to 0 = disabled */
	immr->im_cpm.cp_pbdir |=  PB_ENET_TENA;
	return (0);
}

/* ------------------------------------------------------------------------- */

void	reset_phy(void)
{
	uchar c;

#ifdef DEBUG
	printf ("### Switch on Ethernet for SCC2 ###\n");
#endif
	c = pic_read  (0x61);
#ifdef DEBUG
	printf ("Old PIC read: reg_61 = 0x%02x\n", c);
#endif
	c |=  0x40;	/* disable COM3 */
	c &= ~0x80;	/* enable Ethernet */
	pic_write (0x61, c);
#ifdef DEBUG
	c = pic_read  (0x61);
	printf ("New PIC read: reg_61 = 0x%02x\n", c);
#endif
	udelay(1000);
}

/*-----------------------------------------------------------------------
 * Keyboard Controller
 */
/* command codes */
#define	KEYBD_CMD_READ_KEYS	0x01
#define KEYBD_CMD_READ_VERSION	0x02
#define KEYBD_CMD_READ_STATUS	0x03
#define KEYBD_CMD_RESET_ERRORS	0x10

/* Number of bytes returned from Keyboard Controller */
#define KEYBD_VERSIONLEN	2	/* version information */
#define	KEYBD_DATALEN		9	/* normal key scan data	*/

static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
static uchar kbd_data[KEYBD_DATALEN];
uchar keybd_env[2*KEYBD_DATALEN+1];

#ifdef CONFIG_PREBOOT
static int key_match (uchar *);
#endif

void misc_init_r (bd_t *bd)
{
	uchar val, errcd;
	int i;

	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);

	/* Read initial keyboard error code */
	val = KEYBD_CMD_READ_STATUS;
	i2c_write (&kbd_addr, 1, &val, 1);
	i2c_read  (&kbd_addr, 1, &errcd, 1);
	if (errcd) {
		printf ("KEYBD: Error %02X\n", errcd);
	}

	/* Reset error code and verify */
	val = KEYBD_CMD_RESET_ERRORS;
	i2c_write (&kbd_addr, 1, &val, 1);
	val = KEYBD_CMD_READ_STATUS;
	i2c_write (&kbd_addr, 1, &val, 1);
	i2c_read  (&kbd_addr, 1, &val, 1);

	if (val) {	/* permanent error, report it */
		printf ("*** Keyboard error code %02X ***\n", val);
		sprintf (keybd_env, "%02X", val);
		setenv ("keybd", keybd_env);
		return;
	}

	/* Read Version */
	val = KEYBD_CMD_READ_VERSION;
	i2c_write (&kbd_addr, 1, &val, 1);
	i2c_read  (&kbd_addr, 1, kbd_data, KEYBD_VERSIONLEN);
	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);

	/* Read keys */
	val = KEYBD_CMD_READ_KEYS;
	i2c_write (&kbd_addr, 1, &val, 1);
	i2c_read  (&kbd_addr, 1, kbd_data, KEYBD_DATALEN);

	for (i=0; i<KEYBD_DATALEN; ++i) {
		sprintf(keybd_env+i+i, "%02X", kbd_data[i]);
	}
	setenv ("keybd", keybd_env);

#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
	if (key_match(kbd_data)) {
		char *s = getenv ("key_cmd");
		setenv ("preboot", s);
	} else {
		setenv ("preboot", NULL);	/* delete any existing definition */
	}
#endif	/* CONFIG_PREBOOT */
}

/*-----------------------------------------------------------------------
 * Check if pressed key(s) match magic sequence
 */
#ifdef CONFIG_PREBOOT
static int key_match (uchar *kbd_data)
{
	uchar compare[KEYBD_DATALEN];
	uchar extra;
	uchar *str, *nxt;
	int i;

	memcpy (compare, kbd_data, KEYBD_DATALEN);

	extra = 0;

	for (str=getenv ("key_magic"); str != NULL; str = (*nxt) ? nxt+1 : nxt) {
		uchar c;
		int k;

		c = (uchar)simple_strtoul(str, (char **)(&nxt), 16);

		if (str == nxt) {	/* invalid character */
			break;
		}

		/*
		 * Check if this key matches the input.
		 * Set matches to zero, so they match only once
		 * and we can find duplicates or extra keys
		 */
		for (k=0; k<KEYBD_DATALEN; ++k) {
			if (compare[k] == '\0')	/* only non-zero entries */
				continue;
			if (c == compare[k]) {	/* found matching key */
				compare[k] = '\0';
				break;
			}
		}
		if (k == KEYBD_DATALEN) {
			extra = 1;		/* unmatched key */
		}
	}

	/*
	 * A full match leaves no keys in the `compare' array,
	 * and has no extra keys
	 */
	
	for (i=0; i<KEYBD_DATALEN; ++i) {
		if (compare[i])
			break;
	}

	return ((i == KEYBD_DATALEN) && (extra == 0));
}
#endif

/*-----------------------------------------------------------------------
 * Board Special Commands: PIC read/write
 */
#if (CONFIG_COMMANDS & CFG_CMD_BSP)

void do_pic (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	uchar reg, val;

	switch (argc) {
	case 3:			/* PIC read reg */
		if (strcmp(argv[1],"read") != 0)
			break;

		reg = simple_strtoul(argv[2], NULL, 16);

		printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg));

		return;
	case 4:			/* PIC write reg val */
		if (strcmp(argv[1],"write") != 0)
			break;

		reg = simple_strtoul(argv[2], NULL, 16);
		val = simple_strtoul(argv[3], NULL, 16);

		printf ("PIC write: reg %02x val 0x%02x: %02x => ",
			reg, val, pic_read (reg));
		pic_write (reg, val);
		printf ("%02x\n\n", pic_read (reg));

		return;
	default:
		break;
	}
	printf ("Usage:\n%s\n", cmdtp->usage);
}

#endif	/* CFG_CMD_BSP */

/*-----------------------------------------------------------------------
 * Utilities
 */

uchar pic_read (uchar reg)
{
	return (i2c_reg_read(CFG_I2C_PICIO_ADDR, reg));
}

void pic_write (uchar reg, uchar val)
{
	i2c_reg_write(CFG_I2C_PICIO_ADDR, reg, val);
}
