


/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H


/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8240		1
#define CONFIG_SANDPOINT	1
#define USE_DINK32		1

#define CONFIG_BAUDRATE		115200
#define CONFIG_DRAM_SPEED	100   /* MHz      */
#define CONFIG_BOOTCOMMAND	""    /* autoboot command */
#define CONFIG_BOOTARGS		" "

#define CONFIG_COMMANDS  (CONFIG_CMD_DFL & ~CFG_CMD_NET)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		1        /* undef to save memory     */
#define CFG_PROMPT		":>"        /* Monitor Command Prompt   */
#define CFG_CBSIZE		256     /* Console I/O Buffer Size  */
#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		8       /* max number of command args   */
#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
#define CFG_LOAD_ADDR		0x00100000  /* default load address */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000

#if defined (USE_DINK32)
  #define CFG_MONITOR_LEN	0x00020000
  #define CFG_MONITOR_BASE	0x00090000
  #define CFG_RAMBOOT		1
  #define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  #define CFG_INIT_RAM_END	(CFG_INIT_RAM_ADDR + 0x10000)	/* End of used area in DPRAM  */
  #define CFG_INIT_DATA_SIZE	256 				/* size in bytes reserved for initial data */
  #define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
  #define CFG_INIT_SP_OFFSET	CFG_INIT_DATA_OFFSET
#else
  #undef  CFG_RAMBOOT
#endif

#define CFG_FLASH_BASE		0xFFF00000
#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom */
#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00008000	/* Offset of Environment Sector	*/
#define CFG_ENV_SIZE		0x00004000	/* Total Size of Environment Sector */

#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()  */

#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM   */

#define CFG_EUMB_ADDR		0xFC000000

#define CFG_ISA_MEM		0xFD000000
#define CFG_ISA_IO		0xFE000000

#define CFG_FLASH_RANGE_BASE	0xFF000000  /* flash memory address range */
#define CFG_FLASH_RANGE_SIZE	0x01000000
#define FLASH_BASE0_PRELIM	0xFFF80000  /* sandpoint flash    */
#define FLASH_BASE1_PRELIM	0xFF000000  /* PMC onboard flash*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */


#define CFG_WINBOND_83C553      1           /*has a winbond bridge  */
#define CFG_USE_WINBOND_IDE     0           /*use winbond 83c553 internal ide controller */
#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800  /*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900  /*ide config addr */
#define CFG_NS87308_BADDR_10    1


#define CFG_NS_PC87308UL        1           /* Nat Semi super-io controller on ISA bus */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */


#define CFG_ROMNAL		7       /*rom/flash next access time*/
#define CFG_ROMFAL		11      /*rom/flash access time*/

#define CFG_REFINT		430     /* no of clock cycles between CBR refresh cycles*/
/* the following are for SDRAM only*/
#define CFG_BSTOPRE		121     /* Burst To Precharge, sets open page interval */
#define CFG_REFREC		8       /* Refresh to activate interval */
#define CFG_RDLAT		3       /* data latency from read command */
#define CFG_PRETOACT		3       /* Precharge to activate interval */
#define CFG_ACTTOPRE		5       /* Activate to Precharge interval */
#define CFG_ACTTORW		3	/* Activate to R/W */
#define CFG_SDMODE_CAS_LAT	2       /* SDMODE CAS latency */
#define CFG_SDMODE_WRAP		0       /* SDMODE wrap type */
#define CFG_SDMODE_BURSTLEN	2       /* SDMODE Burst length 2=4, 3=8 */

#define CFG_REGISTERD_TYPE_BUFFER   1

/* memory bank settings*/
/* only bits 20-29 are actually used from these vales to set the stare/end address
   the upper two bits will be 0, and the lower 20 bits will be set to
   0x00000 for a start address, or 0xfffff for an end address*/

#define CFG_BANK0_START		0x00000000
#define CFG_BANK0_END		0x03ffffff
#define CFG_BANK1_START		0x04000000
#define CFG_BANK1_END		0x07ffffff
#define CFG_BANK2_START		0x08000000
#define CFG_BANK2_END		0x0bffffff
#define CFG_BANK3_START		0x0c000000
#define CFG_BANK3_END		0x0fffffff
#define CFG_BANK4_START		0x00000000
#define CFG_BANK4_END		0x00000000
#define CFG_BANK5_START		0x00000000
#define CFG_BANK5_END		0x00000000
#define CFG_BANK6_START		0x00000000
#define CFG_BANK6_END		0x00000000
#define CFG_BANK7_START		0x00000000
#define CFG_BANK7_END		0x00000000

/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CFG_BANK_ENABLE		0x01

#define CFG_ODCR		0xff /* configures line driver impedances,
                                        see 8240 book for bit definitions */
#define CFG_PGMAX		0x32 /* how long the 8240 retains the currently accessed page in memory
                                        see 8240 book for details*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2           /* max number of memory banks       */
#define CFG_MAX_FLASH_SECT	20          /* max number of sectors on one chip    */

#define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)  */
#define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)  */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16          /* For all MPC8xx CPUs          */



/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD           0x01        /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM           0x02        /* Software reboot          */


/* values according to the manual */

#define CONFIG_DRAM_50MHZ       1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1


#define CONFIG_DISK_SPINUP_TIME 1000000


#endif  /* __CONFIG_H */
