/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/processor.h>

#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */

/* these hardware addresses are pretty bogus, please change them to
   suit your needs */

/* first ethernet */
#define CONFIG_ETHADDR          00:11:22:33:44:55

/* next two ethernet hwaddrs */
#define CONFIG_ETH1ADDR		00:11:22:33:44:66
#define CONFIG_ETH2ADDR		00:11:22:33:44:77

#define CONFIG_ENV_OVERWRITE

#define CONFIG_74xx		1	/* This is a MPC74xx		*/
#define CONFIG_EVB64260		1	/* ...on an EVB64260 board	*/

#define CONFIG_BAUDRATE		38400 	/* console baudrate = 115kbps	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

/*
 * The following defines let you select what serial you want to use
 * for your console driver.
 *
 * what to do:
 * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
 * cable onto the second DUART channel, change the CFG_DUART port from 1
 * to 0 below.
 *
 * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
 */
#undef	CONFIG_MPSC
#define CONFIG_MPSC_PORT        0

/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_ETHER_PORT	0

#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						     \
	"bootp 1000000; " 						     \
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "  \
	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	"$(netmask):$(hostname):eth0:none; "\
	"bootm" 

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_ALTIVEC                  /* undef to disable             */

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
				 CONFIG_BOOTP_BOOTFILESIZE)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "	        /* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
#define CFG_BUS_HZ      100000000       /* bus speed - 100 mhz          */

#define CFG_BAUDRATE_TABLE    { 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_RAM_ADDR	0x00df0000     /* above the memtest region */
#define	CFG_INIT_RAM_END	0x0f00
#define	CFG_INIT_DATA_SIZE	64  /* size in bytes reserved for init data */
#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_INIT_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xfff00000
#define	CFG_MONITOR_LEN		(256 << 10)   /* Reserve 128 kB for Monitor */
#define CFG_MONITOR_BASE        CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */

/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS		4
#define CFG_DFL_GT_REGS		0x14000000
#define CFG_GT_REGS		0xf0000000
#define CFG_DEV0_SPACE		(CFG_GT_REGS + _8M)
#define CFG_DEV1_SPACE		(CFG_GT_REGS + (2 * _8M))
#define CFG_DEV2_SPACE		(CFG_GT_REGS + (3 * _8M))
#define CFG_DEV3_SPACE		(CFG_GT_REGS + (4 * _8M))

#define CFG_DEV0_SIZE		_8M
#define CFG_DEV1_SIZE		_8M
#define CFG_DEV2_SIZE		_8M
#define CFG_DEV3_SIZE		_16M

#define CFG_DUART_IO            CFG_DEV2_SPACE
#define CFG_DUART_CHAN		1            /* channel to use for console */
#define CFG_INIT_CHAN1
#define	CFG_INIT_CHAN2

#define	SRAM_BASE               CFG_DEV0_SPACE
#define	SRAM_SIZE               0x00100000      /* 1 MB of sram */

#define CFG_CPU_CLK		300000000
#define CFG_BUS_CLK		133000000

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* do we even need the MMU?  probably not... */
#undef  CFG_MMU

#if 0
/* SDRAM */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT1L
#define CFG_DBAT0U CFG_IBAT1U

/* address range for accessing the Gal. board registers/debug leds */
#define CFG_IBAT1L (CFG_DEBUG_BASE | BATL_RW | BATL_COHERENT | BATL_GUARDED)
#define CFG_IBAT1U (CFG_DEBUG_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U

/* GT regs, flash, all the devices */
#define CFG_IBAT2L (CFG_DEV_REGS | BATL_CACHEINHIBIT | BATL_RO)
#define CFG_IBAT2U (CFG_DEV_REGS | BATU_VS | BATU_VP | BATU_BL_16M)
#define CFG_DBAT2L CFG_IBAT0L
#define CFG_DBAT2U CFG_IBAT0U

/* nothing */
#define CFG_IBAT3L (BATL_NO_ACCESS)
#define CFG_IBAT3U (BATU_INVALID)
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U

#else
/* values that DINK sets up...currently the kernel expects these values */

/* SDRAM */
#define CFG_IBAT0L 0x00000032
#define CFG_IBAT0U 0x00001fff
#define CFG_DBAT0L 0x00000032
#define CFG_DBAT0U 0x00001fff

/* address range for accessing the Gal. board registers/debug leds */
#define CFG_IBAT1L 0x10000032
#define CFG_IBAT1U 0x10001fff
#define CFG_DBAT1L 0x10000032
#define CFG_DBAT1U 0x10001fff

/* GT regs, flash, all the devices */
#define CFG_IBAT2L 0x00000012
#define CFG_IBAT2U 0xc0001fff
#define CFG_DBAT2L 0x00000012
#define CFG_DBAT2U 0xc0001fff

/* nothing */
#define CFG_IBAT3L 0xf0000012
#define CFG_IBAT3U 0xf0001fff
#define CFG_DBAT3L 0xf0000032
#define CFG_DBAT3U 0xf0001fff
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)  /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x40000
#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * L2CR setup -- make sure this is right for your board!
 * look in include/mpc74xx.h for the defines used here
 */
#define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
                   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
