/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <ppc4xx.h>
#include <asm/processor.h>


/* PCI Registers.
 */
#define PCI_VENDOR_ID       0x00
#define PCI_COMMAND         0x04
#define PCI_CLASS_REVISION  0x08
#define PCI_LATENCY_TIMER   0x0d
#define PCI_BASE_ADDRESS_0  0x10
#define PCI_BASE_ADDRESS_1  0x14
#define PCI_BASE_ADDRESS_2  0x18
#define PCI_CFDA_PSM        0x43

#define PCI_COMMAND_IO      0x1
#define PCI_COMMAND_MEM     0x2
#define PCI_COMMAND_MASTER  0x4

#define CBIO_MASK   -128


u_long pci9054_iobase;


#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */


/*-----------------------------------------------------------------------------+
|  Subroutine:  PCI_Read_CFG_Reg
|  Description: Read a PCI configuration register
|  Inputs:
|               BusDevFunc      PCI Bus+Device+Function number
|               Reg             Configuration register number
|               Width           Number of bytes to read (1, 2, or 4)
|  Return value:
|               (unsigned int)  Value of the configuration register read.
|                      For reads shorter than 4 bytes, return value
|                      is LSB-justified
+-----------------------------------------------------------------------------*/
unsigned int     PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width)
{
  unsigned long      conAdrVal;
  unsigned long      val;
  unsigned long      Value;

  /* generate coded value for CON_ADR register */

  conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000;

  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;

  /* Note: *pResult comes back as -1 if machine check happened */
  val = in32r(PCI_PRIMARY_CDR);

  /* shift to position */
  switch (Width)
    {
    case 1:
      val >>= ((Reg & 0x03) * 8);
      val &= 0xff;
      Value = (unsigned char) val;
      break;
    case 2:
      val >>= ((Reg & (int)(0x02) ) * 8);
      val &= 0xffff;
      Value = (unsigned short) val;
      break;
    case 4:
      Value = (unsigned long) val;
      break;
    }

  out32r(PCI_PRIMARY_CAR, 0);

  if ((*(unsigned long *)0x50000304) & 0x60000000)
    {
      /* clear pci master/target abort bits */
      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
    }

  return (Value);
}

/*-----------------------------------------------------------------------------+
|  Subroutine:  PCI_Write_CFG_Reg
|  Description: Write a PCI configuration register.
|  Inputs:
|               BusDevFunc      PCI Bus+Device+Function number
|               Reg             Configuration register number
|               Value           Configuration register value
|               Width           Number of bytes to write (1, 2, or 4)
|  Return value:
|               0       Successful
| Updated for pass2 errata #6. Need to disable interrupts and clear the
| PCICFGADR reg after writing the PCICFGDATA reg.
+-----------------------------------------------------------------------------*/
int    PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width)
{
  unsigned long      conAdrVal;
  unsigned long      val;
  
  conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000;
  
  /* shift to position */
  {
    unsigned long	ldata;
    int	mask;
    
    val = PCI_Read_CFG_Reg(BusDevFunc, Reg & ~3, 4);
    
    switch (Width)
      {
      case 1:
        mask = 0x000000ff;
        ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x03) * 8);
        mask <<= ((Reg & 0x03) * 8);
        Value = (val & ~mask) | ldata;
        break;
      case 2:
        mask = 0x0000ffff;
        ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x02) * 8);
        mask <<= ((Reg & (int)0x02) * 8);
        Value = (val & ~mask) | ldata;
        break;
      case 4:
        break;
      }
    
  }
  
  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
  
  out32r(PCI_PRIMARY_CDR, Value);
  
  out32r(PCI_PRIMARY_CAR, 0);
  
  /* clear pci master/target abort bits */
  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
  
  return (0);
}


/*-----------------------------------------------------------------------
 */

void pci9054_init(void)
{
  int status = 0;
  unsigned char timer;
  
  /*
   * Configure PLX PCI9054
   */
  status = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_COMMAND, 2);
  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEM;
  PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_COMMAND, status, 2);
  
  /* Check the latency timer for values >= 0x60.
   */
  timer = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 1);
  if (timer < 0x60)
    {
      PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60, 1);
    }
  
  /* Set I/O base register.
   */
  PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE, 4);
  pci9054_iobase = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, 4);
  
  pci9054_iobase &= CBIO_MASK;
  pci9054_iobase += 0xc0000000; // test-only
  
  if (pci9054_iobase == 0xffffffff)
    {
      printf("Error: Can not set I/O base register.\n");
      return;
    }
}
